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CAT25M02 Schematic ( PDF Datasheet ) - ON Semiconductor

Teilenummer CAT25M02
Beschreibung 2Mb SPI Serial CMOS EEPROM
Hersteller ON Semiconductor
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Gesamt 14 Seiten
CAT25M02 Datasheet, Funktion
CAT25M02
2 Mb SPI Serial CMOS
EEPROM
Description
The CAT25M02 is a 2M−bit Serial CMOS EEPROM device
internally organized as 256Kx8 bits. This features a 256−byte page
write buffer and supports the Serial Peripheral Interface (SPI)
protocol. The device is enabled through a Chip Select (CS) input. In
addition, the required bus signals are clock input (SCK), data input
(SI) and data output (SO) lines. The HOLD input may be used to pause
any serial communication with the CAT25M02 device. The device
features software and hardware write protection, including partial as
well as full array protection.
On−Chip ECC (Error Correction Code) makes the device suitable
for high reliability applications.
Features
5 / 10 MHz SPI Compatible
Supply Voltage Range: 1.7 V to 5.5 V
SPI Modes (0,0) & (1,1)
256−byte Page Write Buffer
Additional Identification Page with Permanent Write Protection
Self−timed Write Cycle
Hardware and Software Protection
Block Write Protection – Protect 1/4, 1/2 or Entire EEPROM Array
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial and Extended Temperature Range
8−lead SOIC and 8−ball WLCSP Packages and Die Sales*
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
VCC
SI
CS
WP
HOLD
SCK
CAT25M02
SO
VSS
Figure 1. Functional Symbol
*Please contact factory for Die Sales Information
www.onsemi.com
SOIC−8
V SUFFIX
CASE 751BD
WLCSP−8
C8A SUFFIX
CASE 567NM
PIN CONFIGURATIONS
CS 1
SO
VCC
HOLD
WP SCK
VSS SI
SOIC (V) (Top View)
VCC
HOLD
CS
SO
SCK
SI
WP
VSS
WLCSP (C8A) (Top View)
Pin Name
CS
SO
WP
VSS
SI
SCK
HOLD
VCC
PIN FUNCTION
Function
Chip Select
Serial Data Output
Write Protect
Ground
Serial Data Input
Serial Clock
Hold Transmission Input
Power Supply
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
November, 2016 − Rev. 2
1
Publication Order Number:
CAT25M02/D






CAT25M02 Datasheet, Funktion
CAT25M02
Status Register
The Status Register, as shown in Table 7, contains a
number of status and control bits.
The RDY (Ready) bit indicates whether the device is busy
with a write operation. This bit is automatically set to 1
during an internal write cycle, and reset to 0 when the device
is ready to accept commands. For the host, this bit is read
only.
The WEL (Write Enable Latch) bit is set/reset by the
WREN/WRDI commands. When set to 1, the device is in a
Write Enable state and when set to 0, the device is in a Write
Disable state.
The BP0 and BP1 (Block Protect) bits determine which
blocks are currently write protected. They are set by the user
with the WRSR command and are non−volatile. The user is
allowed to protect a quarter, one half or the entire memory,
by setting these bits according to Table 8. The protected
blocks then become read−only.
The TWC (Write Cycle Time) bit is set by the user with
the WRSR command and is volatile. When set to 0, the
device is in a standard write mode with optimum ICC write,
when set to 1 the device is in a fast write mode.
Note: The fast write mode is recommended to be used only
with VCC > 2.5 V.
Table 7. STATUS REGISTER
76
WPEN
IPL
5
TWC
4
LIP
The WPEN (Write Protect Enable) bit acts as an enable
for the WP pin. Hardware write protection is enabled when
the WP pin is low and the WPEN bit is 1. This condition
prevents writing to the status register and to the block
protected sections of memory. While hardware write
protection is active, only the non−block protected memory
can be written. Hardware write protection is disabled when
the WP pin is high or the WPEN bit is 0. The WPEN bit, WP
pin and WEL bit combine to either permit or inhibit Write
operations, as detailed in Table 9.
The IPL (Identification Page Latch) bit determines
whether the additional Identification Page (IPL = 1) or main
memory array (IPL = 0) can be accessed both for Read and
Write operations. The IPL bit is set by the user with the
WRSR command and is volatile. The IPL bit is
automatically reset after read/write operations.
The LIP bit is set by the user with the WRSR command
and is non-volatile. When set to 1, the Identification Page is
permanently write protected (locked in Read-only mode).
Note: The IPL and LIP bits cannot be set to 1 using the same
WRSR instruction. If the user attempts to set (“1”) both the
IPL and LIP bit in the same time, these bits cannot be written
and therefore they will remain unchanged.
3210
BP1
BP0
WEL
RDY
Table 8. BLOCK PROTECTION BITS
Status Register Bits
BP1 BP0
00
01
10
11
Array Address Protected
None
30000h−3FFFFh
20000h−3FFFFh
00000h−3FFFFh
Protection
No Protection
Quarter Array Protection
Half Array Protection
Full Array Protection
Table 9. WRITE PROTECT CONDITIONS
WPEN
WP
0X
0X
1 Low
1 Low
X High
X High
WEL
0
1
0
1
0
1
Protected Blocks
Protected
Protected
Protected
Protected
Protected
Protected
Unprotected Blocks
Protected
Writable
Protected
Writable
Protected
Writable
Status Register
Protected
Writable
Protected
Protected
Protected
Writable
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6

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CAT25M02 pdf, datenblatt
PIN # 1
IDENTIFICATION
TOP VIEW
CAT25M02
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD
ISSUE O
E1 E
SYMBOL
A
A1
b
c
D
E
E1
e
h
L
θ
MIN
1.35
0.10
0.33
0.19
4.80
5.80
3.80
0.25
0.40
NOM
1.27 BSC
MAX
1.75
0.25
0.51
0.25
5.00
6.20
4.00
0.50
1.27
D
A1
A
eb
SIDE VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
h
θ
L
END VIEW
c
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