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PDF NTMFD4C85N Data sheet ( Hoja de datos )
| Número de pieza | NTMFD4C85N | |
| Descripción | Dual N-Channel SO8FL | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NTMFD4C85N
PowerPhase, Dual
N-Channel SO8FL
30 V, High Side 25 A / Low Side 49 A
Features
• Co−Packaged Power Stage Solution to Minimize Board Space
• Minimized Parasitic Inductances
• Optimized Devices to Reduce Power Losses
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Applications
• DC−DC Converters
• System Voltage Rails
• Point of Load
www.onsemi.com
V(BR)DSS
Q1 Top FET
30 V
Q2 Bottom FET
30 V
RDS(ON) MAX
3.0 mW @ 10 V
4.3 mW @ 4.5 V
0.8 mW @ 10 V
1.2 mW @ 4.5 V
ID MAX
25 A
49 A
D1 (3, 4, 9)
Figure 1. Typical Application Circuit
100
95
90
85
80 VIN = 12 V
VOUT = 1.2 V
75 VGS = 5 V
FSW = 300 kHz
70 TA = 25°C
0 5 10 15 20 25 30
LOAD CURRENT (A)
Figure 2. Typical Efficiency Performance
POWERPHASEGEVB Evaluation Board
© Semiconductor Components Industries, LLC, 2014
December, 2014 − Rev. 0
1
(1) G1
(2) S1
SW (5, 6, 7)
(8) G2
S2 (10)
PIN CONNECTIONS
D1 4
D1 3 9 10
D1 S2
S1 2
5 SW
6 SW
7 SW
G1 1
8 G2
(Bottom View)
MARKING
DIAGRAM
1
DFN8
CASE 506CR
4C85N
AYWZZ
1
4C85N = Specific Device Code
A = Assembly Location
Y = Year
W = Work Week
ZZ = Lot Traceability
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
Publication Order Number:
NTMFD4C85N/D
1 page  
NTMFD4C85N
TYPICAL CHARACTERISTICS − Q1
160
140
120
100
80
60
40
20
0
0
3.8 V
4.0 V − 10 V
VGS = 3.6 V
TJ = 25°C
3.4 V
3.2 V
3.0 V
2.8 V
2.6 V
2.4 V
12 3 45
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 3. On−Region Characteristics
160
VDS = 3 V
140
120
100
80
60
40 25°C
20
0
125°C
−55°C
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 4. Transfer Characteristics
10
9
8
TJ = 25°C
ID = 20 A
7
6
5
4
3
2
1
2 3 4 5 6 7 8 9 10
VGS, GATE VOLTAGE (V)
Figure 5. On−Resistance vs. Gate−to−Source
Voltage
1.8
1.6 VGS = 10 V
ID = 20 A
1.4
1.2
1.0
0.8
0.6
0.4
0.2
−50
−25 0 25 50 75 100 125
TJ, JUNCTION TEMPERATURE (°C)
Figure 7. On−Resistance Variation with
Temperature
150
6
5
4
VGS = 4.5 V
3
VGS = 10 V
2
1 TJ = 25°C
0
10 20 30 40 50 60 70 80
ID, DRAIN CURRENT (A)
Figure 6. On−Resistance vs. Drain Current and
Gate Voltage
4000
3500
3000
2500
2000
1500
CISS
COSS
VGS = 0 V
TJ = 25°C
f = 1 MHz
1000
500
0
0
CRSS
5 10 15 20 25
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 8. Capacitance Variation
30
www.onsemi.com
5
5 Page 
NTMFD4C85N
PACKAGE DIMENSIONS
DFN8 5x6, 1.27P PowerPhase FET
CASE 506CR
ISSUE B
2X
0.20 C
DA
D1
87 6 5
B 2X
0.20 C
PIN ONE
IDENTIFIER
ÉÉÉÉ
1 2 34
TOP VIEW
0.10 C
E1 E
A
c
0.10 C
NOTE 4
SIDE VIEW
DETAIL A
C
SEATING
PLANE
NOTE 6
8X b
0.10 M C A B
1 0.05 M C NOTE 3
5X L
6X b2
1
DETAIL A
D2
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSIONS b AND b1 APPLY TO PLATED TERMINAL AND ARE
MEASURED BETWEEN 0.15 AND 0.25 MM FROM THE TIPS.
4. COPLANARITY APPLIES TO THE EXPOSED PADS AS WELL AS THE
TERMINALS.
5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
6. SEATING PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED
AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
4X
h
A1
0.10 M C A B
MILLIMETERS
DIM MIN MAX
A 0.90 1.10
A1 0.00 0.05
b 0.40 0.60
b2 0.40 0.60
c 0.20 0.30
D 5.15 BSC
D1 4.90 5.10
D2 3.70 3.90
D3 2.96 3.16
E 6.15 BSC
E1 5.80 6.00
E2 2.37 2.57
E3 1.05 1.25
E4 1.36 1.56
e 1.27 BSC
G 0.625 BSC
G1 1.615 BSC
h −−− 12 _
L 0.34 0.59
L2 1.68 1.93
E3
0.10 M C A B
E4
L2
e/2
e
BOTTOM VIEW
G1
G
E2
D3
SUPPLEMENTAL
BOTTOM VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
1.27
PITCH
0.62
5.50
4.05
5X
0.75
0.54
2.07
1.22
2.67
6.50
1.66 5X
0.76
0.23
0.71 2.31
0.98
6X
0.65
4.10
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
11
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