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PDF EPF011A Data sheet ( Hoja de datos )
| Número de pieza | EPF011A | |
| Descripción | MCU | |
| Fabricantes | Explore | |
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User Guide — EPF011ACD_UG V0.2
Generic MCU with 64K Embedded Flash
EPF011A/EPF011C/EPF011D
User Guide
V0.2
Revised: Nov. 07, 2007
Original Release Date: Jan. 16, 2006
Explore, Taiwan
Explore reserves the right to make changes without further notice to any products herein to improve reliability, function or design.
Explore does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it
convey any license under its patent rights nor the rights of others. Explore products are not designed, intended, or authorized for use as
components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any
other application in which the failure of the Explore product could create a situation where personal injury or death may occur. Should
Buyer purchase or use Explore products for any such unintended or unauthorized application, Buyer shall indemnify and hold Explore
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and
reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or
unauthorized use, even if such claim alleges that Explore was negligent regarding the design or manufacture of the part.
Explore
Confidential Proprietary
NON-DISCLOSURE AGREEMENT REQUIRED
1
1 page  
User Guide — EPF011ACD_UG V0.2
8.2
8.2.1
8.2.2
8.2.3
8.3
8.3.1
SFR Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Port 1 register (p1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Port 1 Direction register (p1d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Key Interrupt Selection register (kbi_en) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Other Related SFR Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Interrupt Enable register 0 (ien0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Section 9 Serial Port
9.1
9.2
9.3
9.3.1
9.3.2
9.3.3
9.3.4
9.4
9.4.1
9.4.2
Serial Interface modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Multiprocessor Communication of Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Special Function Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Serial Port Control register (S0con). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Serial Port Data Buffer register (s0buf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Serial Port Baud Rate Reload register low (s0rell) . . . . . . . . . . . . . . . . . . . . . .51
Serial Port Baud Rate Reload register high (s0relh) . . . . . . . . . . . . . . . . . . . .51
Other Related SFR Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Interrupt Enable register 0 (ien0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Power Management Control register (pcon). . . . . . . . . . . . . . . . . . . . . . . . . . .53
Section 10 Timer
10.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
10.2 SFR Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
10.2.1 Timer Status register (tim_sta) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
10.2.2 Timer Selection register (tim_sel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
10.2.3 Timer I/O register (tim_io) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
10.2.4 Timer Control register (tim_ctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
10.2.5 Prescale register (tim_pre) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
10.2.6 Timer register (timer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
10.3 Other Related SFR Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
10.3.1 Interrupt Enable register 0 (ien0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Section 11 PWM
11.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
11.2 SFR Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
11.2.1 PWM Control register (pwm_ctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
11.2.2 PWM Enable register (pwm_en) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Explore
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3
5 Page 
Section 1 Introduction
User Guide — EPF011ACD_UG V0.2
1.1 Overview
EPF011A/EPF011C/EPF011D is a low cost high performance Micro Controller. The chip integrates 80515
core, 64KB embedded Flash, 256 + 2KB RAM, Timer, Watchdog Timer, Serial Port, 8-bit PWM, SPI, IIC
Slave, IIC Master, 10-bit ADC, USB 1.1, Remote Decoder, Keyboard Interrupt and GPIO in a single chip.
1.2 Features
• On-chip 80515 core with 64K bytes Flash, 256 bytes Direct RAM and 2K bytes on-chip auxiliary
RAM
• Fast CPU rate (24Mhz). 41.6 ns for shortest instruction
• Programmable CPU clocks from 24 Mhz to 500 Khz
• Programmable crystal start-up cycles from 0 to 4096 cycles
• Supports Idle mode and Stop mode for power saving.
• Supports crystal/CPU wake-up from Stop mode
• Supports In Circuit Flash programming (ICP)
• Supports 2 external interrupts
• Supports keyboard interrupt on 4 GPIO pins.
• On-chip 4 Timers supporting Timer, Pulse Output, Event Counter and Pulse Width Measurement
modes
• On-chip 15-bit programmable Watchdog Timer
• On-chip Serial Port which supports Synchronous mode and 8/9-bit UART modes
• On-chip Serial Peripheral Interface (SPI)
• On-chip 4 channels of 8-bit PWM with programmable repetition rate
• On-chip 4 channels of 10-bit ADC
• On-chip IIC Master and Slave ports with configurable pin outs
• On-chip USB 1.1 which supports end-pint 0, 1 and 2
• On-chip Consumer Infra-Red Remote Receiver (CIR) which supports NEC and Phillips RC-5
protocols
• EPF011A supports 9 General Purpose I/O Ports (total 44 I/O pins). Among them, 6 ports are
open-drain programmable and 2 ports has 20 mA sink capability. All I/O ports are 5V tolerant.
• EPF011D supports 9 General Purpose I/O Ports (total 31 I/O pins). Among them, 6 ports are
open-drain programmable and 2 ports has 20 mA sink capability. All I/O ports are 5V tolerant.
9 Confidential Proprietary
NON-DISCLOSURE AGREEMENT REQUIRED
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet EPF011A.PDF ] | |
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