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PDF ADSP-21478 Data sheet ( Hoja de datos )
| Número de pieza | ADSP-21478 | |
| Descripción | SHARC Processor | |
| Fabricantes | Analog Devices | |
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SHARC Processor
ADSP-21477/ADSP-21478/ADSP-21479
SUMMARY
High performance 32-bit/40-bit floating-point processor
optimized for high performance audio processing
Single-instruction, multiple-data (SIMD) computational
architecture
On-chip memory—up to 5M bits of on-chip RAM, 4M bits of
on-chip ROM
Up to 300 MHz operating frequency
Qualified for automotive applications. See Automotive Prod-
ucts on Page 75
Code compatible with all other members of the SHARC family
The ADSP-2147x processors are available with unique
audio-centric peripherals, such as the digital applications
interface, serial ports, precision clock generators, S/PDIF
transceiver, asynchronous sample rate converters, input
data port, and more.
Factory programmed ROM versions containing latest audio
decoders from Dolby and DTS, available to IP licenses
For complete ordering information, see Ordering Guide on
Page 76.
SIMD Core
Instruction
Cache
DAG1/2
5 Stage
Sequencer
Core
Timer
PEx PEy
FLAGx/IRQx/
TMREXP
JTAG THERMAL
DIODE
Block 0
RAM/ROM
Internal Memory
Block 1
RAM/ROM
Block 2
RAM
Block 3
RAM
DMD
64-BIT
PMD
64-BIT
S
DMD
64-BIT
Core Bus
Cross Bar
PMD 64-BIT
EPD BUS 64-BIT
B0D
64-BIT
B1D
64-BIT
B2D
64-BIT
Internal Memory I/F
IOD0 32-BIT
B3D
64-BIT
PERIPHERAL BUS 32-BIT
IOD1
32-BIT
PERIPHERAL BUS
CORE
FLAGS/
PWM3-1
PCG
C-D
TIMER
1-0
TWI
SPI/B UART
IOD0 BUS
FFT DTCP/
FIR MTM
IIR
SHIFT S/PDIF PCG ASRC PDAP/ SPORT
REG Tx/Rx A-D 3-0 IDP 7-0
7-0
SPEP BUS
CORE PWM
RTC WDT MLB FLAGS 3-0
EP
AMI SDRAM
CTL
DPI Routing/Pins
DPI Peripherals
DAI Routing/Pins
DAI Peripherals
Figure 1. Functional Block Diagram
External Port Pin MUX
Peripherals
External
Port
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADSP-21477/ADSP-21478/ADSP-21479
buses and on-chip instruction cache, the processor can simulta-
neously fetch four operands (two over each data bus) and one
instruction (from the cache), all in a single cycle.
S
SIMD Core
DMD/PMD 64
DAG1
16×32
DAG2
16×32
JTAG FLAG TIMER INTERRUPT CACHE
5 STAGE
PROGRAM SEQUENCER
PM ADDRESS 24
PM DATA 48
PM ADDRESS 32
DM ADDRESS 32
PM DATA 64
DM DATA 64
SYSTEM
I/F
USTAT
4×32-BIT
PX
64-BIT
MULTIPLIER SHIFTER ALU
RF
Rx/Fx
PEx
16×40-BIT
DATA
SWAP
RF
Sx/SFx
PEy
16×40-BIT
ALU
SHIFTER MULTIPLIER
MRF
80-BIT
MRB
80-BIT
ASTATx
STYKx
ASTATy
STYKy
MSB
80-BIT
MSF
80-BIT
Figure 2. SHARC Core Block Diagram
Instruction Cache
The processor includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and four
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
cache allows full speed execution of core looped operations such
as digital filter multiply-accumulates, and FFT butterfly
processing.
Data Address Generators with Zero-Overhead Hardware
Circular Buffer Support
The processor’s two data address generators (DAGs) are used
for indirect addressing and implementing circular data buffers
in hardware. Circular buffers allow efficient programming of
delay lines and other data structures required in digital signal
processing, and are commonly used in digital filters and Fourier
transforms. The two DAGs of the processors contain sufficient
registers to allow the creation of up to 32 circular buffers (16
primary register sets, 16 secondary). The DAGs automatically
handle address pointer wraparound, reduce overhead, increase
performance, and simplify implementation. Circular buffers can
start and end at any memory location.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the
processors can conditionally execute a multiply, an add, and a
subtract in both processing elements while branching and fetch-
ing up to four 32-bit values from memory—all in a single
instruction.
Variable Instruction Set Architecture (VISA)
In addition to supporting the standard 48-bit instructions from
previous SHARC processors, the processors support new
instructions of 16 and 32 bits. This feature, called Variable
Instruction Set Architecture (VISA), drops redundant/unused
Rev. C | Page 5 of 76 | July 2013
5 Page 
ADSP-21477/ADSP-21478/ADSP-21479
Digital Peripheral Interface (DPI)
The digital peripheral interface provides connections to two
serial peripheral interface ports (SPI), one universal asynchro-
nous receiver-transmitter (UART), 12 flags, a 2-wire interface
(TWI), three PWM modules (PWM3–1), and two general-
purpose timers.
Serial Peripheral (Compatible) Interface (SPI)
The SPI is an industry-standard synchronous serial link,
enabling the SPI-compatible port to communicate with other
SPI compatible devices. The SPI consists of two data pins, one
device select pin, and one clock pin. It is a full-duplex synchro-
nous serial interface, supporting both master and slave modes.
The SPI port can operate in a multi-master environment by
interfacing with up to four other SPI-compatible devices, either
acting as a master or slave device. The SPI-compatible periph-
eral implementation also features programmable baud rate and
clock phase and polarities. The SPI-compatible port uses open
drain drivers to support a multi-master configuration and to
avoid data contention.
UART Port
The processors provide a full-duplex Universal Asynchronous
Receiver/Transmitter (UART) port, which is fully compatible
with PC-standard UARTs. The UART port provides a simpli-
fied UART interface to other peripherals or hosts, supporting
full-duplex, DMA-supported, asynchronous transfers of serial
data. The UART also has multiprocessor communication capa-
bility using 9-bit address detection. This allows it to be used in
multidrop networks through the RS-485 data interface
standard. The UART port also includes support for 5 to 8 data
bits, 1 or 2 stop bits, and none, even, or odd parity. The UART
port supports two modes of operation:
• PIO (programmed I/O) – The processor sends or receives
data by writing or reading I/O-mapped UART registers.
The data is double-buffered on both transmit and receive.
• DMA (direct memory access) – The DMA controller trans-
fers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. The UART has two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates.
The UART port's baud rate, serial data format, error code gen-
eration and status, and interrupts are programmable:
• Support for bit rates ranging from (fPCLK/1,048,576) to
(fPCLK/16) bits per second.
• Support for data formats from 7 to 12 bits per frame.
• Both transmit and receive operations can be configured to
generate maskable interrupts to the processor.
In conjunction with the general-purpose timer functions, auto-
baud detection is supported.
Pulse-Width Modulation
The PWM module is a flexible, programmable, PWM waveform
generator that can be programmed to generate the required
switching patterns for various applications related to motor and
engine control or audio power control. The PWM generator can
generate either center-aligned or edge-aligned PWM wave-
forms. In addition, it can generate complementary signals on
two outputs in paired mode or independent signals in non-
paired mode (applicable to a single group of four PWM
waveforms).
The entire PWM module has four groups of four PWM outputs
generating 16 PWM outputs in total. Each PWM group pro-
duces two pairs of PWM signals on the four PWM outputs.
The PWM generator is capable of operating in two distinct
modes while generating center-aligned PWM waveforms: single
update mode or double update mode. In single update mode the
duty cycle values are programmable only once per PWM period.
This results in PWM patterns that are symmetrical about the
midpoint of the PWM period. In double update mode, a second
updating of the PWM registers is implemented at the midpoint
of the PWM period. In this mode, it is possible to produce
asymmetrical PWM patterns that produce lower harmonic dis-
tortion in three-phase PWM inverters.
PWM signals can be mapped to the external port address lines
or to the DPI pins.
Timers
The processors have a total of three timers: a core timer that can
generate periodic software interrupts and two general-purpose
timers that can generate periodic interrupts and be inde-
pendently set to operate in one of three modes:
• Pulse waveform generation mode
• Pulse width count/capture mode
• External event watch dog mode
The core timer can be configured to use FLAG3 as a timer
expired signal, and the general-purpose timers have one bidirec-
tional pin and four registers that implement its mode of
operation: a 6-bit configuration register, a 32-bit count register,
a 32-bit period register, and a 32-bit pulse width register. A sin-
gle control and status register enables or disables the general-
purpose timer.
2-Wire Interface Port (TWI)
The TWI is a bidirectional 2-wire serial bus used to move 8-bit
data while maintaining compliance with the I2C bus protocol.
The TWI master incorporates the following features:
• 7-bit addressing
• Simultaneous master and slave operation on multiple
device systems with support for multi-master data
arbitration
• Digital filtering and timed event processing
• 100 kbps and 400 kbps data rates
• Low interrupt rate
Rev. C | Page 11 of 76 | July 2013
11 Page | ||
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| PDF Descargar | [ Datasheet ADSP-21478.PDF ] | |
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