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ADSP-21477 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADSP-21477
Beschreibung SHARC Processor
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADSP-21477 Datasheet, Funktion
SHARC Processor
ADSP-21477/ADSP-21478/ADSP-21479
SUMMARY
High performance 32-bit/40-bit floating-point processor
optimized for high performance audio processing
Single-instruction, multiple-data (SIMD) computational
architecture
On-chip memory—up to 5M bits of on-chip RAM, 4M bits of
on-chip ROM
Up to 300 MHz operating frequency
Qualified for automotive applications. See Automotive Prod-
ucts on Page 75
Code compatible with all other members of the SHARC family
The ADSP-2147x processors are available with unique
audio-centric peripherals, such as the digital applications
interface, serial ports, precision clock generators, S/PDIF
transceiver, asynchronous sample rate converters, input
data port, and more.
Factory programmed ROM versions containing latest audio
decoders from Dolby and DTS, available to IP licenses
For complete ordering information, see Ordering Guide on
Page 76.
SIMD Core
Instruction
Cache
DAG1/2
5 Stage
Sequencer
Core
Timer
PEx PEy
FLAGx/IRQx/
TMREXP
JTAG THERMAL
DIODE
Block 0
RAM/ROM
Internal Memory
Block 1
RAM/ROM
Block 2
RAM
Block 3
RAM
DMD
64-BIT
PMD
64-BIT
S
DMD
64-BIT
Core Bus
Cross Bar
PMD 64-BIT
EPD BUS 64-BIT
B0D
64-BIT
B1D
64-BIT
B2D
64-BIT
Internal Memory I/F
IOD0 32-BIT
B3D
64-BIT
PERIPHERAL BUS 32-BIT
IOD1
32-BIT
PERIPHERAL BUS
CORE
FLAGS/
PWM3-1
PCG
C-D
TIMER
1-0
TWI
SPI/B UART
IOD0 BUS
FFT DTCP/
FIR MTM
IIR
SHIFT S/PDIF PCG ASRC PDAP/ SPORT
REG Tx/Rx A-D 3-0 IDP 7-0
7-0
SPEP BUS
CORE PWM
RTC WDT MLB FLAGS 3-0
EP
AMI SDRAM
CTL
DPI Routing/Pins
DPI Peripherals
DAI Routing/Pins
DAI Peripherals
Figure 1. Functional Block Diagram
External Port Pin MUX
Peripherals
External
Port
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. C
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However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
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Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
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ADSP-21477 Datasheet, Funktion
ADSP-21477/ADSP-21478/ADSP-21479
bits within the 48-bit instruction to create more efficient and
compact code. The program sequencer supports fetching these
16-bit and 32-bit instructions from both internal and external
SDRAM memory. This support is not extended to the asynchro-
nous memory interface (AMI). Source modules need to be built
using the VISA option, in order to allow code generation tools
to create these more efficient opcodes.
On-Chip Memory
The processors contain varying amounts of internal RAM and
internal ROM which is shown in Table 3 through Table 5. Each
block can be configured for different combinations of code and
data storage. Each memory block supports single-cycle, inde-
pendent accesses by the core processor and I/O processor.
The processor’s SRAM can be configured as a maximum of
160k words of 32-bit data, 320k words of 16-bit data, 106.7k
words of 48-bit instructions (or 40-bit data), or combinations of
different word sizes up to 5M bits. All of the memory can be
accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit
floating-point storage format is supported that effectively dou-
bles the amount of data that may be stored on-chip. Conversion
between the 32-bit floating-point and 16-bit floating-point
formats is performed in a single instruction. While each mem-
ory block can store combinations of code and data, accesses are
most efficient when one block stores data using the DM bus for
transfers, and the other block stores instructions and data using
the PM bus for transfers.
Using the DM bus and PM buses, with one bus dedicated to a
memory block, assures single-cycle execution with two data
transfers. In this case, the instruction must be available in the
cache.
The memory maps in Table 3 through Table 5 display the inter-
nal memory address space of the processors. The 48-bit space
section describes what this address range looks like to an
instruction that retrieves 48-bit memory. The 32-bit section
describes what this address range looks like to an instruction
that retrieves 32-bit memory.
Table 3. ADSP-21477 Internal Memory Space (2M bits)
IOP Registers 0x0000 0000–0x0003 FFFF
Long Word (64 Bits)
Extended Precision Normal or
Instruction Word (48 Bits)
Block 0 ROM (Reserved)
0x0004 0000–0x0004 7FFF
Block 0 ROM (Reserved)
0x0008 0000–0x0008 AAA9
Reserved
0x0004 8000–0x0004 8FFF
Reserved
0x0008 AAAA–0x0008 BFFF
Block 0 SRAM
Block 0 SRAM
0x0004 9000–0x0004 BFFF
0x0008 C000–0x0008 FFFF
Reserved
Reserved
0x0004 C000–0x0004 FFFF
0x0009 000–0x0009 5554
Block 1 ROM (Reserved)
Block 1 ROM (Reserved)
0x0005 0000–0x0005 7FFF
0x000A 0000–0x000A AAA9
Reserved
Reserved
0x0005 8000–0x0005 8FFF
0x000A AAAA–0x000A BFFF
Block 1 SRAM
Block 1 SRAM
0x0005 9000–0x0005 BFFF
0x000A C000–0x000A FFFF
Reserved
Reserved
0x0005 C000–0x0005 FFFF
0x000B 0000–0x000B 5554
Block 2 SRAM
Block 2 SRAM
0x0006 0000–0x0006 0FFF
0x000C 0000–0x000C 1554
Reserved
Reserved
0x0006 1000– 0x0006 FFFF
0x000C 1555–0x000D 5554
Block 3 SRAM
Block 3 SRAM
0x0007 0000–0x0007 0FFF
0x000E 0000–0x000E 1554
Reserved
Reserved
0x0007 1000–0x0007 FFFF
0x000E 1555–0x000F 5554
Normal Word (32 Bits)
Block 0 ROM (Reserved)
0x0008 0000–0x0008 FFFF
Reserved
0x0009 0000–0x0009 1FFF
Block 0 SRAM
0x0009 2000–0x0009 7FFF
Reserved
0x0009 8000–0x0009 FFFF
Block 1 ROM (Reserved)
0x000A 0000–0x000AFFFF
Reserved
0x000B 0000–0x000B 1FFF
Block 1 SRAM
0x000B 2000–0x000B 7FFF
Reserved
0x000B 8000–0x000B FFFF
Block 2 SRAM
0x000C 0000–0x000C 1FFF
Reserved
0x000C 2000–0x000D FFFF
Block 3 SRAM
0x000E 0000–0x000E 1FFF
Reserved
0x000E 2000–0x000F FFFF
Short Word (16 Bits)
Block 0 ROM (Reserved)
0x0010 0000–0x0011 FFFF
Reserved
0x0012 0000–0x0012 FFFF
Block 0 SRAM
0x0012 4000–0x0012 FFFF
Reserved
0x0013 0000–0x0013 FFFF
Block 1 ROM (Reserved)
0x0014 0000–0x0015 FFFF
Reserved
0x0016 0000–0x0016 3FFF
Block 1 SRAM
0x0016 4000–0x0016 FFFF
Reserved
0x0017 0000–0x0017 FFFF
Block 2 SRAM
0x0018 0000–0x0018 3FFF
Reserved
0x0018 4000–0x001B FFFF
Block 3 SRAM
0x001C 0000–0x001C 3FFF
Reserved
0x001C 4000–0x001F FFFF
Rev. C | Page 6 of 76 | July 2013

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ADSP-21477 pdf, datenblatt
ADSP-21477/ADSP-21478/ADSP-21479
Shift Register
The shift register can be used as a serial to parallel data con-
verter. The shift register module consists of an 18-stage serial
shift register, 18-bit latch, and three-state output buffers. The
shift register and latch have separate clocks. Data is shifted into
the serial shift register on the positive-going transitions of the
shift register serial clock (SR_SCLK) input. The data in each
flip-flop is transferred to the respective latch on a positive-going
transition of the shift register latch clock (SR_LAT) input.
The shift register’s signals can be configured as follows.
• The SR_SCLK can come from any of the SPORT0–7 SCLK
outputs, PCGA/B clock, any of the DAI pins (1–8), and one
dedicated pin (SR_SCLK).
• The SR_LAT can come from any of SPORT0–7 frame sync
outputs, PCGA/B frame sync, any of the DAI pins (1–8),
and one dedicated pin (SR_LAT).
• The SR_SDI input can from any of SPORT0–7 serial data
outputs, any of the DAI pins (1–8), and one dedicated pin
(SR_SDI).
Note that the SR_SCLK, SR_LAT, and SR_SDI inputs must
come from same source except in the case of where SR_SCLK
comes from PCGA/B or SR_SCLK and SR_LAT come from
PCGA/B.
If SR_SCLK comes from PCGA/B, then SPORT0–7 generates
the SR_LAT and SR_SDI signals. If SR_SCLK and SR_LAT
come from PCGA/B, then SPORT0–7 generates the
SR_SDI signal.
I/O PROCESSOR FEATURES
The I/O processor provides up to 65 channels of DMA as well as
an extensive set of peripherals.
DMA Controller
The DMA controller operates independently and invisibly to
the processor core, allowing DMA operations to occur while the
core is simultaneously executing its program instructions. DMA
transfers can occur between the processor’s internal memory
and its serial ports, the SPI-compatible (serial peripheral inter-
face) ports, the IDP (input data port), the parallel data
acquisition port (PDAP) or the UART.
Up to 65 channels of DMA are available on the processors as
shown in Table 9.
Programs can be downloaded using DMA transfers. Other
DMA features include interrupt generation upon completion of
DMA transfers, and DMA chaining for automatic linked DMA
transfers.
Table 9. DMA Channels
Peripheral
SPORTs
PDAP
SPI
UART
DMA Channels
16
8
2
2
Table 9. DMA Channels (Continued)
Peripheral
External Port
Accelerators
Memory-to-Memory
MediaLB1
1 Automotive models only.
DMA Channels
2
2
2
31
Delay Line DMA
The processor provides delay line DMA functionality. This
allows processor reads and writes to external delay line buffers
(and therefore to external memory) with limited core
interaction.
Scatter/Gather DMA
The processor provides scatter/gather DMA functionality. This
allows processor DMA reads/writes to/from noncontiguous
memory blocks.
FFT Accelerator
The FFT accelerator implements radix-2 complex/real input,
complex output FFTs with no core intervention. The FFT accel-
erator runs at the peripheral clock frequency.
FIR Accelerator
The FIR (finite impulse response) accelerator consists of a 1024
word coefficient memory, a 1024 word deep delay line for the
data, and four MAC units. A controller manages the accelerator.
The FIR accelerator runs at the peripheral clock frequency.
IIR Accelerator
The IIR (infinite impulse response) accelerator consists of a
1440 word coefficient memory for storage of biquad coeffi-
cients, a data memory for storing the intermediate data and one
MAC unit. A controller manages the accelerator. The IIR accel-
erator runs at the peripheral clock frequency.
Watchdog Timer (WDT)
The processors include a 32-bit watchdog timer that can be used
to implement a software watchdog function. A software watch-
dog can improve system reliability by forcing the processor to a
known state through generation of a system reset if the timer
expires before being reloaded by software. Software initializes
the count value of the timer, and then enables the timer.
The WDT is used to supervise the stability of the system soft-
ware. When used in this way, software reloads the WDT in a
regular manner so that the downward counting timer never
expires. An expiring timer then indicates that system software
might be out of control.
The WDT resets both the core and the internal peripherals.
Software must be able to determine if the watch dog was the
source of the hardware reset by interrogating a status bit in the
watch dog timer control register.
Rev. C | Page 12 of 76 | July 2013

12 Page





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