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ADG5206 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADG5206
Beschreibung 8-/16-Channel Multiplexers
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 28 Seiten
ADG5206 Datasheet, Funktion
Data Sheet
FEATURES
Latch-up proof
3.5 pF off source capacitance
Off drain capacitance
ADG5206: 64 pF
ADG5207: 33 pF
0.35 pC typical charge injection
±0.02 nA on channel leakage
Low on resistance: 155 Ω typical
±9 V to ±22 V dual-supply operation
9 V to 40 V single-supply operation
VSS to VDD analog signal range
Human body model (HBM) ESD rating
ADG5206: 8 kV all pins
ADG5207: 8 kV I/O port to supplies
APPLICATIONS
Automatic test equipment
Data acquisition
Instrumentation
Avionics
Battery monitoring
Communication systems
GENERAL DESCRIPTION
The ADG5206 and ADG5207 are monolithic CMOS analog
multiplexers comprising 16 single channels and 8 differential
channels, respectively. The ADG5206 switches one of sixteen
inputs to a common output, as determined by the 4-bit binary
address lines, A0, A1, A2, and A3. The ADG5207 switches one
of eight differential inputs to a common differential output, as
determined by the 3-bit binary address lines, A0, A1, and A2.
An EN input on both devices enables or disables the device. When
EN is low, the device is disabled and all channels switch off. The
ultralow capacitance and charge injection of these switches make
them ideal solutions for data acquisition and sample-and-hold
applications, where low glitch and fast settling are required. Fast
switching speed coupled with high signal bandwidth make these
devices suitable for video signal switching.
Each switch conducts equally well in both directions when on,
and each switch has an input signal range that extends to the
power supplies. In the off condition, signal levels up to the
supplies are blocked.
Rev. A
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High Voltage, Latch-Up Proof,
8-/16-Channel Multiplexers
ADG5206/ADG5207
FUNCTIONAL BLOCK DIAGRAMS
ADG5206
S1
D
S16
1-OF-16
DECODER
A0 A1 A2 A3 EN
Figure 1.
ADG5207
S1A
DA
S8A
S1B
S8B
1-OF-8
DECODER
DB
A0 A1 A2 EN
Figure 2.
The ADG5206/ADG5207 do not have VL pins; instead, an on-chip
voltage generator generates the logic power supply internally.
PRODUCT HIGHLIGHTS
1. Trench Isolation Guards Against Latch-Up. A dielectric trench
separates the P and N channel transistors to prevent latch-up
even under severe overvoltage conditions.
2. Optimal switch design for low charge injection, low switch
capacitance, and low leakage currents.
3. The ADG5206 achieves 8 kV HBM ESD specification on
all external pins, while the ADG5207 achieves 8 kV on the
I/O port to supply pins, 2 kV on the I/O port to I/O port
pins, and 8 kV on all other pins.
4. Dual-Supply Operation. For applications where the analog
signal is bipolar, the ADG5206/ADG5207 can be operated
from dual supplies of up to ±22 V.
5. Single-Supply Operation. For applications where the
analog signal is unipolar, the ADG5206/ADG5207 can be
operated from a single rail power supply of up to 40 V.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2012–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com






ADG5206 Datasheet, Funktion
ADG5206/ADG5207
Data Sheet
Parameter
CD (Off )
ADG5206
ADG5207
CD (On), CS (On)
ADG5206
ADG5207
POWER REQUIREMENTS
IDD
ISS
VDD/VSS
25°C
−40°C to −40°C to −40°C to
+60°C
+85°C
+125°C Unit
Test Conditions/Comments
62
pF typ
VS = 0 V, f = 1 MHz
32
pF typ
VS = 0 V, f = 1 MHz
67
35
50
70
0.001
110
1
±9/±22
pF typ
pF typ
µA typ
µA max
µA typ
µA max
V min/V max
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = +22 V, VSS = −22 V
Digital inputs = 0 V or VDD
Digital inputs = 0 V or VDD
GND = 0 V
1 The off channel leakage delta is calculated using the maximum of VS = +15 V and VD = −15 V, or VS = −15 V and VD = +15 V.
2 The on channel leakage delta is calculated using the maximum of VS = VD = +15 V, or VS = VD = −15 V.
3 Guaranteed by design; not subject to production test.
12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 3.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
25°C
−40°C to −40°C to
+60°C
+85°C
350
−40°C to
+125°C
0 V to VDD
Unit
V
Ω typ
On-Resistance Match Between
Channels, ∆RON
On-Resistance Flatness, RFLAT (ON)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
500 560 610 700 Ω max
5 Ω typ
20 21 22 24 Ω max
170 Ω typ
280 310 335 370 Ω max
±0.005
nA typ
Match Between Channels, ΔLeakage,
IS (Off )1
Drain Off Leakage, ID (Off )
±0.1
0.01
±0.15
±0.2
±0.4
0.015
nA max
nA typ
ADG5206
ADG5207
Match Between Channels, ΔLeakage,
ID (Off ), ADG5207 Only
Channel On Leakage, ID (On), IS (On)
ADG5206
ADG5207
Match Between Channels, ΔLeakage,
ID (On), IS (On)2
±0.02
±0.1
±0.02
±0.1
0.015
±0.02
±0.1
±0.02
±0.1
0.01
±0.25
±0.25
±0.25
±0.2
±0.6
±0.4
±0.6
±0.4
±3.3
±1.7
0.015
nA typ
nA max
nA typ
nA max
nA typ
nA typ
±3.3 nA max
nA typ
±1.7 nA max
0.03 nA typ
Rev. A | Page 6 of 28
Test Conditions/Comments
VS = 0 V to 10 V, IS = −1 mA;
see Figure 32
VDD = 10.8 V, VSS = 0 V
VS = 0 V to 10 V, IS = −1 mA
VS = 0 V to 10 V, IS = −1 mA
VDD = +13.2 V, VSS = 0 V
VS = 1 V/10 V, VD = 10 V/1 V;
see Figure 33
VS = 1 V/10 V, VD = 1 V/10 V;
see Figure 33
VS = VD = 1 V/10 V; see Figure 34

6 Page









ADG5206 pdf, datenblatt
ADG5206/ADG5207
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Data Sheet
VDD 1
NC 2
NC 3
S16 4
S15 5
S14 6
S13 7
S12 8
S11 9
S10 10
S9 11
GND 12
NC 13
A3 14
ADG5206
TOP VIEW
(Not to Scale)
28 D
27 VSS
26 S8
25 S7
24 S6
23 S5
22 S4
21 S3
20 S2
19 S1
18 EN
17 A0
16 A1
15 A2
NOTES
1. NO CONNECT. NOT INTERNALLY CONNECTED.
Figure 3. ADG5206 Pin Configuration (TSSOP)
S16 1
S15 2
S14 3
S13 4
S12 5
S11 6
S10 7
S9 8
ADG5206
TOP VIEW
(Not to Scale)
24 S8
23 S7
22 S6
21 S5
20 S4
19 S3
18 S2
17 S1
NOTES
1. NO CONNECT. NOT INTERNALLY CONNECTED.
2. THE EXPOSED PAD IS CONNECTED INTERNALLY. FOR
INCREASED RELIABILITY OF THE SOLDER JOINTS AND
MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED
THAT THE PAD BE SOLDERED TO THE SUBSTRATE, VSS.
Figure 4. ADG5206 Pin Configuration (LFCSP)
Table 8. ADG5206 Pin Function Descriptions
Pin No.
TSSOP LFCSP
Mnemonic Description
1
2, 3, 13
4
5
6
7
8
9
10
11
12
14
15
16
17
18
31
12, 13, 26, 27,
28, 30, 32
1
2
3
4
5
6
7
8
9
10
11
14
15
16
19 17
20 18
21 19
22 20
23 21
24 22
25 23
26 24
27 25
28 29
NA Exposed Pad
VDD
NC
S16
S15
S14
S13
S12
S11
S10
S9
GND
A3
A2
A1
A0
EN
S1
S2
S3
S4
S5
S6
S7
S8
VSS
D
Most Positive Power Supply Potential.
No Connect. Not internally connected.
Source Terminal 16. This pin can be an input or an output.
Source Terminal 15. This pin can be an input or an output.
Source Terminal 14. This pin can be an input or an output.
Source Terminal 13. This pin can be an input or an output.
Source Terminal 12. This pin can be an input or an output.
Source Terminal 11. This pin can be an input or an output.
Source Terminal 10. This pin can be an input or an output.
Source Terminal 9. This pin can be an input or an output.
Ground (0 V) Reference.
Logic Control Input.
Logic Control Input.
Logic Control Input.
Logic Control Input.
Active High Digital Input. When this pin is low, the device is disabled and all switches are turned
off. When this pin is high, the Ax logic inputs determine which switch is turned on.
Source Terminal 1. This pin can be an input or an output.
Source Terminal 2. This pin can be an input or an output.
Source Terminal 3. This pin can be an input or an output.
Source Terminal 4. This pin can be an input or an output.
Source Terminal 5. This pin can be an input or an output.
Source Terminal 6. This pin can be an input or an output.
Source Terminal 7. This pin can be an input or an output.
Source Terminal 8. This pin can be an input or an output.
Most Negative Power Supply Potential. In single-supply applications, this pin can be connected
to ground.
Drain Terminal. This pin can be an input or an output.
The exposed pad is connected internally. For increased reliability of the solder joints and
maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS.
Rev. A | Page 12 of 28

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