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PDF EDJ4216EFBG Data sheet ( Hoja de datos )
| Número de pieza | EDJ4216EFBG | |
| Descripción | 256M words x 16 bits 4G bits DDR3L SDRAM | |
| Fabricantes | Elpida Memory | |
| Logotipo |  |
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COVER
PRELIMINARY DATA SHEET
4G bits DDR3L SDRAM
EDJ4204EFBG (1024M words × 4 bits)
EDJ4208EFBG (512M words × 8 bits)
EDJ4216EFBG (256M words × 16 bits)
Specifications
• Density: 4G bits
• Organization
— 128M words × 4 bits × 8 banks (EDJ4204EFBG)
— 64M words × 8 bits × 8 banks (EDJ4208EFBG)
— 32M words × 16 bits × 8 banks (EDJ4216EFBG)
• Package
— 78-ball FBGA (EDJ4204EFBG, EDJ4208EFBG)
— 96-ball FBGA (EDJ4216EFBG)
— Lead-free (RoHS compliant) and Halogen-free
• Power supply: 1.35V (typ)
— VDD = 1.283V to 1.45V
— Backward compatible for VDD, VDDQ
= 1.5V ± 0.075V
• Data rate
— 1600Mbps/1333Mbps (max)
• 1KB page size
— Row address: A0 to A15
— Column address: A0 to A9, A11 (EDJ4204EFBG)
A0 to A9 (EDJ4208EFBG)
• 2KB page size (EDJ4216EFBG)
— Row address: A0 to A14
— Column address: A0 to A9
• Eight internal banks for concurrent operation
• Burst length (BL): 8 and 4 with Burst Chop (BC)
• Burst type (BT):
— Sequential (8, 4 with BC)
— Interleave (8, 4 with BC)
• /CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11
• /CAS Write Latency (CWL): 5, 6, 7, 8
• Precharge: auto precharge option for each burst
access
• Driver strength: RZQ/7, RZQ/6 (RZQ = 240Ω)
• Refresh: auto-refresh, self-refresh
• Refresh cycles
— Average refresh period
7.8µs at 0°C ≤ TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
• Operating case temperature range
— TC = 0°C to +95°C
Features
• Double-data-rate architecture: two data transfers per
clock cycle
• The high-speed data transfer is realized by the 8 bits
prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Posted /CAS by programmable additive latency for
better command and data bus efficiency
• On-Die Termination (ODT) for better signal quality
— Synchronous ODT
— Dynamic ODT
— Asynchronous ODT
• Multi Purpose Register (MPR) for pre-defined pattern
read out
• ZQ calibration for DQ drive and ODT
• Programmable Partial Array Self-Refresh (PASR)
• /RESET pin for Power-up sequence and reset function
• SRT range:
— Normal/extended
• Programmable Output driver impedance control
Document. No. E1922E11 (Ver. 1.1)
Date Published September 2012 (K) Japan
Printed in Japan
URL: http://www.elpida.com
©Elpida Memory, Inc. 2012
1 page  
EDJ4204EFBG, EDJ4208EFBG, EDJ4216EFBG
CONTENTS
Specifications ........................................................................................................................................ 1
Features ................................................................................................................................................ 1
Ordering Information ............................................................................................................................. 2
Part Number .......................................................................................................................................... 2
Detailed Information .............................................................................................................................. 2
Pin Configurations ................................................................................................................................. 3
1. Electrical Conditions ...................................................................................................................... 6
1.1 Absolute Maximum Ratings ..............................................................................................................6
1.2 Operating Temperature Condition ....................................................................................................6
1.3 Recommended DC Operating Conditions ........................................................................................7
1.4 IDD and IDDQ Measurement Conditions ..........................................................................................8
2. Electrical Specifications ............................................................................................................... 19
2.1 DC Characteristics .......................................................................................................................... 19
2.2 Pin Capacitance .............................................................................................................................. 20
2.3 Standard Speed Bins ...................................................................................................................... 21
3. Package Drawing ......................................................................................................................... 25
3.1 78-ball FBGA .................................................................................................................................. 25
3.2 96-ball FBGA .................................................................................................................................. 26
4. Recommended Soldering Conditions .......................................................................................... 27
Preliminary Data Sheet E1922E11 (Ver. 1.1)
5
5 Page 
EDJ4204EFBG, EDJ4208EFBG, EDJ4216EFBG
1.4.2 Basic IDD and IDDQ Measurement Conditions
Table 6: Basic IDD and IDDQ Measurement Conditions
Parameter
Operating one bank
active precharge
current
Operating one bank
active-read-precharge
current
Precharge standby
current
Precharge standby
ODT current
Precharge standby
ODT IDDQ current
Precharge power-down
current slow exit
Precharge power-down
current fast exit
Precharge quiet
standby current
Active standby current
Active power-down
current
Operating burst read
current
Operating burst read
IDDQ current
Symbol
IDD0
IDD1
IDD2N
IDD2NT
IDDQ2NT
IDD2P0
IDD2P1
IDD2Q
IDD3N
IDD3P
IDD4R
IDDQ4R
Description
CKE: H; External clock: on; tCK, nRC, nRAS, CL: see Table 5; BL: 8*1; AL: 0; /CS: H
between ACT and PRE; Command, address, bank address inputs: partially toggling
according to Table 7; Data I/O: MID-LEVEL; DM: stable at 0;
Bank activity: cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 7);
Output buffer and RTT: enabled in MR*2; ODT signal: stable at 0; Pattern details: see
Table 7
CKE: H; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 5; BL: 8*1, *6; AL:
0; /CS: H between ACT, RD and PRE; Command, address, bank address inputs, data
I/O: partially toggling according to Table 8;
DM: stable at 0; Bank activity: cycling with one bank active at a time: 0,0,1,1,2,2,...
(see Table 8); Output buffer and RTT: enabled in MR*2; ODT Signal: stable at 0;
Pattern details: see Table 8
CKE: H; External clock: on; tCK, CL: see Table 5 BL: 8*1; AL: 0; /CS: stable at 1;
Command, address, bank address Inputs: partially toggling according to Table 9;
data I/O: MID-LEVEL; DM: stable at 0; bank activity: all banks closed; output buffer
and RTT: enabled in mode registers*2; ODT signal: stable at 0; pattern details: see
Table 9
CKE: H; External clock: on; tCK, CL: see Table 5; BL: 8*1; AL: 0; /CS: stable at 1;
Command, address, bank address Inputs: partially toggling according to Table 10;
data I/O: MID-LEVEL; DM: stable at 0; bank activity: all banks closed; output buffer
and RTT: enabled in MR*2; ODT signal: toggling according to Table 10; pattern
details: see Table 10
Same definition like for IDD2NT, however measuring IDDQ current instead of IDD
current
CKE: L; External clock: on; tCK, CL: see Table 5; BL: 8*1; AL: 0; /CS: stable at 1;
Command, address, bank address inputs: stable at 0; data I/O: MID-LEVEL; DM:
stable at 0; bank activity: all banks closed; output buffer and RTT: EMR*2; ODT
signal: stable at 0; precharge power down mode: slow exit*3
CKE: L; External clock: on; tCK, CL: see Table 6; BL: 8*1; AL: 0; /CS: stable at 1;
Command, address, bank address Inputs: stable at 0; data I/O: MID-LEVEL;
DM:stable at 0; bank activity: all banks closed; output buffer and RTT: enabled in
MR*2; ODT signal: stable at 0; precharge power down mode: fast exit*3
CKE: H; External clock: On; tCK, CL: see Table 5; BL: 8*1; AL: 0; /CS: stable at 1;
Command, address, bank address Inputs: stable at 0; data I/O: MID-LEVEL;
DM: stable at 0;bank activity: all banks closed; output buffer and RTT: enabled in
MR*2; ODT signal: stable at 0
CKE: H; External clock: on; tCK, CL: see Table 5; BL: 8*1; AL: 0; /CS: stable at 1;
Command, address, bank address Inputs: partially toggling according to Table 9;
data I/O: MID-LEVEL; DM: stable at 0;
bank activity: all banks open; output buffer and RTT: enabled in MR*2;
ODT signal: stable at 0; pattern details: see Table 9
CKE: L; External clock: on; tCK, CL: see Table 5; BL: 8*1; AL: 0; /CS: stable at 1;
Command, address, bank address inputs: stable at 0; data I/O: MID-LEVEL;
DM:stable at 0; bank activity: all banks open; output buffer and RTT:
enabled in MR*2; ODT signal: stable at 0
CKE: H; External clock: on; tCK, CL: see Table 5; BL: 8*1, *6; AL: 0; /CS: H between
RD; Command, address, bank address Inputs: partially toggling according to
Table 11; data I/O: seamless read
data burst with different data between one burst and the next one according to
Table 11; DM: stable at 0;
bank activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,...
(see Table 11); Output buffer and RTT: enabled in MR*2; ODT signal: stable at 0;
pattern details: see Table 11
Same definition like for IDD4R, however measuring IDDQ current instead of IDD
current
Preliminary Data Sheet E1922E11 (Ver. 1.1)
11
11 Page | ||
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| PDF Descargar | [ Datasheet EDJ4216EFBG.PDF ] | |
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