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EDJ4208EFBG Schematic ( PDF Datasheet ) - Elpida Memory

Teilenummer EDJ4208EFBG
Beschreibung 512M words x 8 bits 4G bits DDR3L SDRAM
Hersteller Elpida Memory
Logo Elpida Memory Logo 




Gesamt 29 Seiten
EDJ4208EFBG Datasheet, Funktion
COVER
PRELIMINARY DATA SHEET
4G bits DDR3L SDRAM
EDJ4204EFBG (1024M words × 4 bits)
EDJ4208EFBG (512M words × 8 bits)
EDJ4216EFBG (256M words × 16 bits)
Specifications
• Density: 4G bits
• Organization
— 128M words × 4 bits × 8 banks (EDJ4204EFBG)
— 64M words × 8 bits × 8 banks (EDJ4208EFBG)
— 32M words × 16 bits × 8 banks (EDJ4216EFBG)
• Package
— 78-ball FBGA (EDJ4204EFBG, EDJ4208EFBG)
— 96-ball FBGA (EDJ4216EFBG)
— Lead-free (RoHS compliant) and Halogen-free
• Power supply: 1.35V (typ)
— VDD = 1.283V to 1.45V
— Backward compatible for VDD, VDDQ
= 1.5V ± 0.075V
• Data rate
— 1600Mbps/1333Mbps (max)
• 1KB page size
— Row address: A0 to A15
— Column address: A0 to A9, A11 (EDJ4204EFBG)
A0 to A9 (EDJ4208EFBG)
• 2KB page size (EDJ4216EFBG)
— Row address: A0 to A14
— Column address: A0 to A9
• Eight internal banks for concurrent operation
• Burst length (BL): 8 and 4 with Burst Chop (BC)
• Burst type (BT):
— Sequential (8, 4 with BC)
— Interleave (8, 4 with BC)
• /CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11
• /CAS Write Latency (CWL): 5, 6, 7, 8
• Precharge: auto precharge option for each burst
access
• Driver strength: RZQ/7, RZQ/6 (RZQ = 240)
• Refresh: auto-refresh, self-refresh
• Refresh cycles
— Average refresh period
7.8µs at 0°C TC +85°C
3.9µs at +85°C < TC +95°C
• Operating case temperature range
— TC = 0°C to +95°C
Features
• Double-data-rate architecture: two data transfers per
clock cycle
• The high-speed data transfer is realized by the 8 bits
prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Posted /CAS by programmable additive latency for
better command and data bus efficiency
• On-Die Termination (ODT) for better signal quality
— Synchronous ODT
— Dynamic ODT
— Asynchronous ODT
• Multi Purpose Register (MPR) for pre-defined pattern
read out
• ZQ calibration for DQ drive and ODT
• Programmable Partial Array Self-Refresh (PASR)
• /RESET pin for Power-up sequence and reset function
• SRT range:
— Normal/extended
• Programmable Output driver impedance control
Document. No. E1922E11 (Ver. 1.1)
Date Published September 2012 (K) Japan
Printed in Japan
URL: http://www.elpida.com
©Elpida Memory, Inc. 2012






EDJ4208EFBG Datasheet, Funktion
EDJ4204EFBG, EDJ4208EFBG, EDJ4216EFBG
1. Electrical Conditions
• All voltages are referenced to VSS (GND)
• Execute power-up and Initialization sequence before proper device operation is achieved.
1.1 Absolute Maximum Ratings
Table 1: Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit Notes
Power supply voltage
VDD
0.4 to +1.975
V 1, 3
Power supply voltage for output
VDDQ
0.4 to +1.975
V 1, 3
Input voltage
VIN 0.4 to +1.975
V1
Output voltage
VOUT
0.4 to +1.975
V1
Reference voltage
VREFCA
0.4 to 0.6 × VDD
V3
Reference voltage for DQ
VREFDQ
0.4 to 0.6 × VDDQ
V
3
Storage temperature
Tstg 55 to +100
°C 1, 2
Power dissipation
PD 1.0
W1
Short circuit output current
IOUT
50
mA 1
Notes: 1.
2.
3.
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
Storage temperature is the case surface temperature on the center/top side of the DRAM.
VDD and VDDQ must be within 300mV of each other at all times; and VREF must be no greater than 0.6 × VDDQ, When
VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.
Caution:
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
1.2 Operating Temperature Condition
Table 2: Operating Temperature Condition
Parameter
Symbol
Rating
Unit Notes
Operating case temperature
TC
0 to +95
°C
1, 2, 3
Notes: 1.
2.
3.
Operating temperature is the case surface temperature on the center/top side of the DRAM.
The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During
operation, the DRAM case temperature must be maintained between 0°C to +85°C under all operating conditions.
Some applications require operation of the DRAM in the Extended Temperature Range between +85°C and +95°C case
temperature. Full specifications are guaranteed in this range, but the following additional conditions apply:
a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9µs. (This double
refresh requirement may not apply for some devices.)
b) If Self-refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual
Self-Refresh mode with Extended Temperature Range capability (MR2 bit [A6, A7] = [0, 1]) or enable the optional Auto
Self-Refresh mode (MR2 bit [A6, A7] = [1, 0]).
Preliminary Data Sheet E1922E11 (Ver. 1.1)
6

6 Page









EDJ4208EFBG pdf, datenblatt
EDJ4204EFBG, EDJ4208EFBG, EDJ4216EFBG
Table 6: Basic IDD and IDDQ Measurement Conditions (cont’d)
Parameter
Symbol
Description
Operating burst write current IDD4W
CKE: H; External clock: on; tCK, CL: see Table 5; BL: 8*1; AL: 0; /CS: H between WR;
command, address, bank address inputs: partially toggling according to Table 12;
data I/O: seamless write data burst with different data between one burst and the next
one according to IDD4W Measurement-Loop Pattern table; DM: stable at 0; bank
activity: all banks open,
WR commands cycling through banks: 0,0,1,1,2,2,.. (see Table 12); Output buffer
and RTT: enabled in MR*2; ODT signal: stable
at H; pattern details: see Table 12
Burst refresh current
IDD5B
CKE: H; External clock: on; tCK, CL, nRFC: see Table 5; BL: 8*1; AL: 0; /CS: H
between REF;
Command, address, bank address Inputs: partially toggling according to Table 13;
data I/O: MID-LEVEL; DM: stable at 0;
bank activity: REF command every nRFC (Table 13); output buffer and RTT: enabled
in MR*2; ODT signal: stable at 0; pattern
details: see Table 13
Self-refresh current: normal
temperature range
IDD6
TC: 0 to 85°C; ASR: disabled*4; SRT:
Normal*5; CKE: L; External clock: off; CK and /CK: L; CL: see Table 5; BL: 8*1;
AL: 0; /CS, command, address, bank address, data I/O: MID-LEVEL; DM: stable
at 0; bank activity: Self-refresh operation; output buffer and RTT: enabled in MR*2;
ODT signal: MID-LEVEL
Self-refresh current: extended
temperature range
IDD6ET
TC: 0 to 95°C; ASR: Disabled*4; SRT: Extended*5; CKE: L; External clock: off; CK
and /CK: L; CL: Table 5; BL: 8*1; AL: 0; /CS, command, address, bank address, data
I/O: MID-LEVEL;
DM: stable at 0; bank activity: Extended temperature self-refresh operation; output
buffer and RTT: enabled in MR*2; ODT signal: MID-LEVEL
Auto self-refresh current
(Optional)
IDD6TC
TC: 0 to 95°C; ASR: Enabled*4; SRT: Normal*5; CKE: L; External clock: off;
CK and /CK: L; CL: Table 5; BL: 8*1; AL: 0; /CS, command, address, bank address,
data I/O: MID-LEVEL; DM: stable at 0; bank activity: Auto self-refresh operation;
output buffer and RTT: enabled in MR*2; ODT signal: MID-LEVEL
Operating bank interleave
read current
IDD7
CKE: H; External clock: on; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see Table 5;
BL: 8*1, *6; AL: CL-1; /CS: H between ACT and RDA; Command, address, bank
address Inputs: partially toggling according to Table 14; data I/O: read data bursts
with different data between one burst and the next one according to Table 14; DM:
stable at 0; bank activity: two times interleaved cycling through banks (0, 1, …7) with
different addressing, see Table 14; output buffer and RTT: enabled in MR*2; ODT
signal: stable at 0; pattern details: see Table 14
RESET low current
IDD8
/RESET: low; External clock: off; CK and /CK: low; CKE: FLOATING; /CS, command,
address, bank address, Data IO: FLOATING; ODT signal: FLOATING
RESET low current reading is valid once power is stable and /RESET has been low
for at least 1ms.
Notes: 1.
2.
3.
4.
5.
6.
Burst Length: BL8 fixed by MRS: MR0 bits [1,0] = [0,0].
MR: Mode Register
Output buffer enable: set MR1 bit A12 = 1 and MR1 bits [5, 1] = [0,1];
RTT_Nom enable: set MR1 bits [9, 6, 2] = [0, 1, 1]; RTT_WR enable: set MR2 bits [10, 9] = [1,0].
Precharge power down mode: set MR0 bit A12= 0 for Slow Exit or MR0 bit A12 = 1 for fast exit.
Auto self-refresh (ASR): set MR2 bit A6 = 0 to disable or 1 to enable feature.
Self-refresh temperature range (SRT): set MR0 bit A7= 0 for normal or 1 for extended temperature range.
Read burst type: nibble sequential, set MR0 bit A3 = 0
Preliminary Data Sheet E1922E11 (Ver. 1.1)
12

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