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C8051F527-IM Schematic ( PDF Datasheet ) - Silicon Laboratories

Teilenummer C8051F527-IM
Beschreibung 8/4/2 kB ISP Flash MCU
Hersteller Silicon Laboratories
Logo Silicon Laboratories Logo 




Gesamt 30 Seiten
C8051F527-IM Datasheet, Funktion
Analog Peripherals
- 12-Bit ADC
Programmable throughput up to 200 ksps
Up to 6/16 external inputs
Data dependent windowed interrupt generator
Built-in temperature sensor
- Comparator
Programmable hysteresis and response time
Configurable as wake-up or reset source
Low current
- POR/Brownout Detector
- Voltage Reference—1.5 and 2.2 V
(programmable)
On-Chip Debug
- On-chip debug circuitry facilitates full-speed, non-
intrusive in-system debug (No emulator required)
- Provides breakpoints, single stepping
- Inspect/modify memory and registers
- Complete development kit
Supply Voltage 2.0 to 5.25 V
- Built-in LDO regulator
High-Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
- Up to 25 MIPS throughput with
25 MHz system clock
- Expanded interrupt handler
C8051F52x/F53x
8/4/2 kB ISP Flash MCU Family
Memory
- 8/4/2 kB Flash; In-system byte programmable in
512 byte sectors
- 256 bytes internal data RAM
Digital Peripherals
- 16/6 port I/O; push-pull or open-drain, 5 V tolerant
- Hardware SPI™, and UART serial port
- LIN 2.1 Controller (Master and Slave capable); no
crystal required
- Three general purpose 16-bit counter/timers
- Programmable 16-bit counter/timer array with three
capture/compare modules, WDT
Clock Sources
- Internal oscillators: 24.5 MHz ±0.5% accuracy sup-
ports UART and LIN-Master operation
- External oscillator: Crystal, RC, C, or Clock
(1 or 2 pin modes)
- Can switch between clock sources on-the-fly
Packages
- 10-Pin DFN (3 x 3 mm)
- 20-pin QFN (4 x 4 mm)
- 20-pin TSSOP
Automotive Qualified
- Temperature Range: –40 to +125 °C
- Compliant to AEC-Q100
Rev. 1.4 4/12
ANALOG
PERIPHERALS
A 12-bit
M
U
200 ksps
X ADC
+
-
TEMP
SENSOR
VOLTAGE
COMPARATOR
VREF VREG
DIGITAL I/O
UART
SPI
PCA
Timer 0
Timer 1
Timer 2
Port 0
Port 1
LIN
24.5 MHz High Precision (±0.5%) Internal Oscillator
HIGH-SPEED CONTROLLER CORE
8/4/2 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
8051 CPU
(25 MIPS)
DEBUG
CIRCUITRY
256 B SRAM
POR WDT
Copyright © 2012 by Silicon Laboratories
C8051F52x/F53x






C8051F527-IM Datasheet, Funktion
C8051F52x/F52xA/F53x/F53xA
19. Programmable Counter Array (PCA0)................................................................ 195
19.1. PCA Counter/Timer ....................................................................................... 196
19.2. Capture/Compare Modules ........................................................................... 197
19.2.1. Edge-triggered Capture Mode............................................................... 198
19.2.2. Software Timer (Compare) Mode.......................................................... 199
19.2.3. High Speed Output Mode...................................................................... 200
19.2.4. Frequency Output Mode ....................................................................... 201
19.2.5. 8-Bit Pulse Width Modulator Mode........................................................ 202
19.2.6. 16-Bit Pulse Width Modulator Mode...................................................... 203
19.3. Watchdog Timer Mode .................................................................................. 203
19.3.1. Watchdog Timer Operation ................................................................... 204
19.3.2. Watchdog Timer Usage ........................................................................ 205
19.4. Register Descriptions for PCA....................................................................... 206
20. Device Specific Behavior .................................................................................... 210
20.1. Device Identification ...................................................................................... 210
20.2. Reset Pin Behavior........................................................................................ 211
20.3. Reset Time Delay .......................................................................................... 211
20.4. VDD Monitors and VDD Ramp Time ............................................................. 211
20.5. VDD Monitor (VDDMON0) High Threshold Setting ....................................... 212
20.6. Reset Low Time............................................................................................. 212
20.7. Internal Oscillator Suspend Mode ................................................................. 212
20.8. UART Pins..................................................................................................... 213
20.9. LIN ................................................................................................................. 213
20.9.1. Stop Bit Check ...................................................................................... 213
20.9.2. Synch Break and Synch Field Length Check........................................ 213
21. C2 Interface .......................................................................................................... 214
21.1. C2 Interface Registers................................................................................... 214
21.2. C2 Pin Sharing .............................................................................................. 216
Document Change List.............................................................................................. 217
Contact Information................................................................................................... 220
6 Rev. 1.4

6 Page









C8051F527-IM pdf, datenblatt
C8051F52x/F52xA/F53x/F53xA
SFR Definition 19.2. PCA0MD: PCA Mode ................................................................ 207
SFR Definition 19.3. PCA0CPMn: PCA Capture/Compare Mode .............................. 208
SFR Definition 19.4. PCA0L: PCA Counter/Timer Low Byte ...................................... 209
SFR Definition 19.5. PCA0H: PCA Counter/Timer High Byte ..................................... 209
SFR Definition 19.6. PCA0CPLn: PCA Capture Module Low Byte ............................. 209
SFR Definition 19.7. PCA0CPHn: PCA Capture Module High Byte ........................... 209
C2 Register Definition 21.1. C2ADD: C2 Address ...................................................... 214
C2 Register Definition 21.2. DEVICEID: C2 Device ID ............................................... 214
C2 Register Definition 21.3. REVID: C2 Revision ID .................................................. 215
C2 Register Definition 21.4. FPCTL: C2 Flash Programming Control ........................ 215
C2 Register Definition 21.5. FPDAT: C2 Flash Programming Data ............................ 215
Rev. 1.4
12

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