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R5F563TEBDFH Schematic ( PDF Datasheet ) - Renesas

Teilenummer R5F563TEBDFH
Beschreibung MCUs
Hersteller Renesas
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Gesamt 30 Seiten
R5F563TEBDFH Datasheet, Funktion
Features
DATASHEET
RX63T Group
Renesas MCUs
R01DS0087EJ0210
Rev.2.10
100-MHz 32-bit RX MCU, on-chip FPU, 165 DMIPS,
Sep 26, 2013
Two 12-bit ADCs (three S/H circuits, double data registers, amplifier, comparator), one 10-bit ADC, simultaneous
sampling on 7 channels using three ADCs, 100 MHz PWM (2 three-phase complementary channels + 4 single-phase
complementary channels or 3 three-phase complementary channels + 1 single-phase complementary channel)
Features
32-bit RX CPU core
Max. operating frequency: 100 MHz
Capable of 165 DMIPS in operation at 100 MHz
Single precision 32-bit IEEE-754 floating point
Two types of multiply-and-accumulation unit (between memories
and between registers)
32-bit multiplier (fastest instruction execution takes one CPU clock
cycle)
Divider (fastest instruction execution takes two CPU clock cycles)
Fast interrupt
CISC Harvard architecture with 5-stage pipeline
Variable-length instructions: Ultra-compact code
Supports the memory protection unit (MPU)
Two types of debugging interfaces: JTAG and FINE (two-line)
Low-power design and architecture
Single 3.3-V supply or single 5-V supply; 3.3-V products can be
used with a 5-V analog power supply
Four low-power modes
On-chip main flash memory, no wait states
100-MHz operation, 10-ns read cycle (no wait states)
Max. 512 Kbytes
User code is programmable by USB, SCI, or JTAG.
On-chip data flash memory
Max. 32 Kbytes, reprogrammable up to 100,000 times
Programming/erasing as background operations (BGOs)
On-chip SRAM, no wait states
Max. 48 Kbytes
For instructions and operands
DMA
DMA: Incorporates four channels
DTC: A single unit can handle transfer on multiple channels.
Reset and supply management
Power-on reset (POR)
Low voltage detection (LVD) with voltage settings
Clock functions
External crystal oscillator or internal PLL for operation at 4 to 12.5
MHz
Internal 125-kHz LOCO
Dedicated 125-kHz LOCO for the IWDT
Independent watchdog timer
125-kHz LOCO clock operation
Useful functions for IEC60730 compliance
Oscillation-stop detection, frequency measurement, CRC, IWDT,
self-diagnostic function for the A/D converter, etc.
External address space
4 CS areas (4 × 1 Mbyte)
Multiplexed address data or separate address lines are selectable per
area.
8- or 16-bit bus space is selectable per area.
PLQP0144KA-A 20 × 20mm, 0.5mm pitch
PLQP0120KA-A 16 × 16mm, 0.5mm pitch
PLQP0112JA-A 20 × 20mm, 0.65mm pitch
PLQP0100KB-A 14 × 14mm, 0.5mm pitch
PLQP0064KB-A 10 × 10mm, 0.5mm pitch
PLQP0048KB-A 7 × 7mm, 0.5mm pitch
Up to 11 communications interfaces
USB 2.0 full-speed function interface (1 channel)
CAN (compliant with ISO11898-1), incorporating 32 mailboxes (1
channel)
SCI with multiple functionalities (5 channels)
Choose from among asynchronous mode, clock-synchronous mode,
smart-card interface mode, simple SPI, simple I2C, and extended
serial mode.
I2C bus interface for SMBus (2 channels)
RSPI for high-speed transfer (2 channels)
Up to twenty 16-bit timers
16-bit MTU3: 100-MHz operation, input capture, output compare,
three-phase complementary PWM waveform output (2 channels),
phase-counting mode (8 channels); complementary PWM does not
burden the CPU.
16-bit GPT: 100-MHz operation, input capture, output compare, 4-
channel single-phase complementary PWM waveform output or 1-
channel three-phase complementary + 1-channel single-phase
complementary output, interlocking with comparator (counter
operation, PWM negation control), detection of abnormal oscillation
frequencies (useful for IEC60730 compliance)
(8 channels); complementary PWM does not burden the CPU.
16-bit CMT (4 channels)
Generation of delays in PWM waveforms (for
products with the product ID code 1)
The timing with which signals on the 16-bit GPT PWM output pin
rise and fall can be controlled with an accuracy of up to 312 ps (in
operation at 100 MHz).
Two A/D converters for 1-MHz operation, total of 8
channels
Simultaneous sampling on 7 channels is possible with three units.
Self-diagnosis function (useful for IEC60730 compliance)
Two 12-bit ADCs: three sample-and-hold circuits, double data
registers, amplifier, comparator (8 channels)
One 10-bit ADC (12 channels)
One A/D converter for 2-MHz operation, total of 20
channels
One 10-bit ADC (20 channels)
10-bit D/A converter: 2 channels
Digital Power Supply Controller-Dedicated
Calculation Function (for products with product ID
code 1)
16-bit fixed-point calculation function that handles compensatory
calculations in the method of digital control for switched-mode
power supplies.
Register write protection function can protect values
in important registers against overwriting.
Up to 110 pins for GPIO
Open drain, switchable driving ability
Operating temp. range
–40C to +85C
–40C to +105C
R01DS0087EJ0210 Rev.2.10
Sep 26, 2013
Page 1 of 182






R5F563TEBDFH Datasheet, Funktion
RX63T Group
1. Overview
Table 1.1
Outline of Specifications (5/7)
Classification
Communication
function
Module/Function
I2C bus interfaces
(RIIC)
CAN module (CAN)
Serial peripheral
interfaces (RSPI)
12-bit A/D converter (S12ADB)
[144-, 120-, 112- and 100-pin versions]
Description
2 channels
Communication formats
I2C bus format/SMBus format
Supports the multi-master
Max. transfer rate: 400 kbps
1 channels
Compliance with the ISO11898-1 specification (standard frame and extended frame)
32 mailboxes per channel
2 channels
RSPI transfer facility
Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select),
and RSPCK (RSPI clock) signals enables serial transfer through SPI operation (four
lines) or clock-synchronous operation (three lines)
Capable of handling serial transfer as a master or slave
Data formats
Switching between MSB first and LSB first
The number of bits in each transfer can be changed to any number of bits from 8 to 16,
or to 20, 24, or 32 bits.
128-bit buffers for transmission and reception
Up to four frames can be transmitted or received in a single transfer operation (with
each frame having up to 32 bits)
Buffered structure
Double buffers for both transmission and reception
Max. transfer rate
In master mode: [144-, 120-, 112- and 100-pin versions]
25 Mbps
[64- and 48-pin versions]
12.5 Mbps
In slave mode: 6.25 Mbps
12 bits (4 channels x 2 unit)
12-bit resolution
Conversion time
1.0 s per channel (clock for S12ADB, PCLKD (A/D conversion clock ADCLK) = 50
MHz, AVCC0 = 4.0 to 5.5 V)
2.0 s per channel (clock for S12ADB, PCLKD (A/D conversion clock ADCLK) = 25
MHz, AVCC0 = 3.0 to 3.6 V)
Operating modes
Scan mode (single-cycle scan mode/continuous scan mode/group scan mode)
Group A priority control (only for the group scan mode)
Sample-and-hold function
A common sample-and-hold circuit for units is included.
Additionally, sample-and-hold circuit for each unit is included. (three channels per unit)
Self-diagnostic function
The self-diagnostic function internally generates three analog input voltages (VREFL0,
VREFH0 x 1/2, VREFH0).
Double trigger mode (duplication of A/D converted data)
Input signal amplification function using programmable gain amplifier (three channels
per unit)
Amplification factors: 2.0 times, 2.5 times, 3.077 times, 3.636 times, 4.0 times, 4.444
times, 5.0 times, 5.714 times, 6.667 times, 10.0 times, 13.333 times (total of 11 steps)
Three ways to start A/D conversion
Conversion can be started by software, a conversion start trigger from a timer (MTU3 or
GPT), or an external trigger signal.
Window comparators (three channels per unit)
R01DS0087EJ0210 Rev.2.10
Sep 26, 2013
Page 6 of 182

6 Page









R5F563TEBDFH pdf, datenblatt
RX63T Group
1. Overview
Table 1.3
List of Products (3/5)
Group Part No.
RX63T R5F563TBBDFP
R5F563TBBDFP
R5F563TEEDFB
R5F563TEEDFA
R5F563TEEDFH
R5F563TEEDFP
R5F563TCEDFB
R5F563TCEDFA
R5F563TCEDFH
R5F563TCEDFP
R5F563TBEDFB
R5F563TBEDFA
R5F563TBEDFH
R5F563TBEDFP
R5F563T6EDFM
R5F563T5EDFM
R5F563T4EDFM
R5F563T6EDFL
R5F563T5EDFL
R5F563T4EDFL
R5F563TEAGFB
R5F563TEAGFB
R5F563TEAGFA
R5F563TEAGFA
R5F563TEAGFH
R5F563TEAGFH
R5F563TEAGFP
R5F563TEAGFP
R5F563TCAGFB
R5F563TCAGFB
Order Part No.
R5F563TBBDFP#V0
Package
PLQP0100KB-A
On-chip ROM
Capacity
256 Kbytes
R5F563TBBDFP#V1 PLQP0100KB-A 256 Kbytes
R5F563TEEDFB#V0 PLQP0144KA-A 512 Kbytes
R5F563TEEDFA#V0 PLQP0120KA-A 512 Kbytes
R5F563TEEDFH#V0 PLQP0112JA-A 512 Kbytes
R5F563TEEDFP#V0 PLQP0100KB-A 512 Kbytes
R5F563TCEDFB#V0 PLQP0144KA-A 384 Kbytes
R5F563TCEDFA#V0 PLQP0120KA-A 384 Kbytes
R5F563TCEDFH#V0 PLQP0112JA-A 384 Kbytes
R5F563TCEDFP#V0 PLQP0100KB-A 384 Kbytes
R5F563TBEDFB#V0 PLQP0144KA-A 256 Kbytes
R5F563TBEDFA#V0 PLQP0120KA-A 256 Kbytes
R5F563TBEDFH#V0 PLQP0112JA-A 256 Kbytes
R5F563TBEDFP#V0 PLQP0100KB-A 256 Kbytes
R5F563T6EDFM#V0 PLQP0064KB-A 64 Kbytes
R5F563T5EDFM#V0 PLQP0064KB-A 48 Kbytes
R5F563T4EDFM#V0 PLQP0064KB-A 32 Kbytes
R5F563T6EDFL#V0 PLQP0048KB-A 64 Kbytes
R5F563T5EDFL#V0 PLQP0048KB-A 48 Kbytes
R5F563T4EDFL#V0 PLQP0048KB-A 32 Kbytes
R5F563TEAGFB#V0 PLQP0144KA-A 512 Kbytes
R5F563TEAGFB#V1 PLQP0144KA-A 512 Kbytes
R5F563TEAGFA#V0 PLQP0120KA-A 512 Kbytes
R5F563TEAGFA#V1 PLQP0120KA-A 512 Kbytes
R5F563TEAGFH#V0 PLQP0112JA-A 512 Kbytes
R5F563TEAGFH#V1 PLQP0112JA-A 512 Kbytes
R5F563TEAGFP#V0 PLQP0100KB-A 512 Kbytes
R5F563TEAGFP#V1 PLQP0100KB-A 512 Kbytes
R5F563TCAGFB#V0 PLQP0144KA-A 384 Kbytes
R5F563TCAGFB#V1 PLQP0144KA-A 384 Kbytes
On-chip RAM
Capacity
Option
24 Kbytes
CAN module
included
24 Kbytes
CAN module
included
48 Kbytes
CAN module
not included
48 Kbytes
CAN module
not included
48 Kbytes
CAN module
not included
48 Kbytes
CAN module
not included
32 Kbytes
CAN module
not included
32 Kbytes
CAN module
not included
32 Kbytes
CAN module
not included
32 Kbytes
CAN module
not included
24 Kbytes
CAN module
not included
24 Kbytes
CAN module
not included
24 Kbytes
CAN module
not included
24 Kbytes
CAN module
not included
8 Kbytes
CAN module
not included
8 Kbytes
CAN module
not included
8 Kbytes
CAN module
not included
8 Kbytes
CAN module
not included
8 Kbytes
CAN module
not included
8 Kbytes
CAN module
not included
48 Kbytes
CAN module
included
48 Kbytes
CAN module
included
48 Kbytes
CAN module
included
48 Kbytes
CAN module
included
48 Kbytes
CAN module
included
48 Kbytes
CAN module
included
48 Kbytes
CAN module
included
48 Kbytes
CAN module
included
32 Kbytes
CAN module
included
32 Kbytes
CAN module
included
Operating Operating
Voltage
Temperature
VCC/
PLLVCC/
VCC_USB
2.7 to 3.6V
AVCC/
AVCC0 3.0
to 3.6V or
4.0 to 5.5V
-40 to +85°C
(D Version)
VCC/
PLLVCC
2.7 to 3.6V
AVCC0 3.0
to 3.6V
VCC/
PLLVCC
4.0 to 5.5V
VCC_USB
3.0 to 3.6V
AVCC/
AVCC0 4.0
to 5.5V
-40 to +105°C
(G Version)*1
R01DS0087EJ0210 Rev.2.10
Sep 26, 2013
Page 12 of 182

12 Page





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