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C8051F715-GMR Schematic ( PDF Datasheet ) - Silicon Laboratories

Teilenummer C8051F715-GMR
Beschreibung Mixed Signal ISP Flash MCU Family
Hersteller Silicon Laboratories
Logo Silicon Laboratories Logo 




Gesamt 30 Seiten
C8051F715-GMR Datasheet, Funktion
Capacitance to Digital Converter
- Supports buttons, sliders, wheels, capacitive prox-
imity, and touch screen sensing
- Up to 38 input channels
- Fast 40 µs per channel conversion time
- 12, 13, 14, or 16-bit output
- Auto-scan and wake-on-touch
- Auto-accumulate 4, 8, 16, 32, or 64 samples
10-Bit Analog to Digital Converter
- Up to 500 ksps
- Up to 16 external single-ended inputs
- VREF from on-chip VREF, external pin or VDD
- Internal or external start of conversion source
- Built-in temperature sensor
Analog Comparator
- Programmable hysteresis and response time
- Configurable as interrupt or reset source
On-Chip Debug
- On-chip debug circuitry facilitates full speed, non-
intrusive in-system debug (no emulator required)
- Provides breakpoints, single stepping,
inspect/modify memory and registers
- Superior performance to emulation systems using
ICE-chips, target pods, and sockets
- Low cost, complete development kit
Supply Voltage 1.8 to 3.6 V
- Built-in voltage supply monitor
C8051F70x/71x
Mixed Signal ISP Flash MCU Family
High-Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
- Up to 25 MIPS throughput with 25 MHz clock
- Expanded interrupt handler
Memory
- 512 bytes internal data RAM (256 + 256)
- Up to 16 kB Flash; In-system programmable in 512-
byte Sectors
- Up to 32-byte data EEPROM
Digital Peripherals
- Up to 54 Port I/O with high sink current
- Hardware enhanced UART, SMBus™ (I2C compati-
ble), and enhanced SPI™ serial ports
- Four general purpose 16-bit counter/timers
- 16-Bit programmable counter array (PCA) with 3
capture/compare modules and enhanced PWM
functionality
- Real time clock mode using timer and crystal
Clock Sources
- 24.5 MHz ±2% Oscillator Supports crystal-less
UART operation
- External oscillator: Crystal, RC, C, or clock
(1 or 2 pin modes)
- Can switch between clock sources on-the-fly; useful
in power saving modes
64-Pin TQFP, 48-Pin TQFP, 48-Pin QFN,
32-Pin QFN, 24-Pin QFN
Temperature Range: –40 to +85 °C
ANALOG
PERIPHERALS
A
M
U
10-bit TEMP
500 ksps SENSOR
X ADC
+
Capacitive
Sense
VOLTAGE
COMPARATOR
DIGITAL I/O
UART
Port 0
SMBus
Port 1
SPI
PCA
Timer 0
Timer 1
Timer 2
Timer 3
Port 2
Port 3
Port 4
Port 5
Port 6.0
– 6.5
24.5 MHz PRECISION INTERNAL OSCILLATOR
HIGH-SPEED CONTROLLER CORE
16 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
8051 CPU
(25 MIPS)
DEBUG
CIRCUITRY
512 B RAM
32 B EEPROM
POR WDT
Rev. 1.0 7/10
Copyright © 2010 by Silicon Laboratories
C8051F70x/71x






C8051F715-GMR Datasheet, Funktion
C8051F70x/71x
28.2.1. Assigning Port I/O Pins to Analog Functions ........................................ 182
28.2.2. Assigning Port I/O Pins to Digital Functions.......................................... 184
28.2.3. Assigning Port I/O Pins to External Event Trigger Functions................ 184
28.3. Priority Crossbar Decoder ............................................................................. 185
28.4. Port I/O Initialization ...................................................................................... 189
28.5. Port Match ..................................................................................................... 192
28.6. Special Function Registers for Accessing and Configuring Port I/O ............. 194
29. Cyclic Redundancy Check Unit (CRC0)............................................................. 211
29.1. 16-bit CRC Algorithm..................................................................................... 212
29.2. 32-bit CRC Algorithm..................................................................................... 213
29.3. Preparing for a CRC Calculation ................................................................... 214
29.4. Performing a CRC Calculation ...................................................................... 214
29.5. Accessing the CRC0 Result .......................................................................... 214
29.6. CRC0 Bit Reverse Feature............................................................................ 218
30. SMBus................................................................................................................... 219
30.1. Supporting Documents .................................................................................. 220
30.2. SMBus Configuration..................................................................................... 220
30.3. SMBus Operation .......................................................................................... 220
30.3.1. Transmitter Vs. Receiver....................................................................... 221
30.3.2. Arbitration.............................................................................................. 221
30.3.3. Clock Low Extension............................................................................. 221
30.3.4. SCL Low Timeout.................................................................................. 221
30.3.5. SCL High (SMBus Free) Timeout ......................................................... 222
30.4. Using the SMBus........................................................................................... 222
30.4.1. SMBus Configuration Register.............................................................. 222
30.4.2. SMB0CN Control Register .................................................................... 226
30.4.2.1. Software ACK Generation ............................................................ 226
30.4.2.2. Hardware ACK Generation ........................................................... 226
30.4.3. Hardware Slave Address Recognition .................................................. 228
30.4.4. Data Register ........................................................................................ 231
30.5. SMBus Transfer Modes................................................................................. 232
30.5.1. Write Sequence (Master) ...................................................................... 232
30.5.2. Read Sequence (Master) ...................................................................... 233
30.5.3. Write Sequence (Slave) ........................................................................ 234
30.5.4. Read Sequence (Slave) ........................................................................ 235
30.6. SMBus Status Decoding................................................................................ 235
31. Enhanced Serial Peripheral Interface (SPI0) ..................................................... 241
31.1. Signal Descriptions........................................................................................ 242
31.1.1. Master Out, Slave In (MOSI)................................................................. 242
31.1.2. Master In, Slave Out (MISO)................................................................. 242
31.1.3. Serial Clock (SCK) ................................................................................ 242
31.1.4. Slave Select (NSS) ............................................................................... 242
31.2. SPI0 Master Mode Operation ........................................................................ 242
31.3. SPI0 Slave Mode Operation .......................................................................... 244
31.4. SPI0 Interrupt Sources .................................................................................. 245
6 Rev. 1.0

6 Page









C8051F715-GMR pdf, datenblatt
C8051F70x/71x
Table 30.4. Hardware Address Recognition Examples (EHACK = 1) ................... 229
Table 30.5. SMBus Status Decoding: Hardware ACK Disabled (EHACK = 0) ...... 236
Table 30.6. SMBus Status Decoding: Hardware ACK Enabled (EHACK = 1) ...... 238
Table 31.1. SPI Slave Timing Parameters ............................................................ 253
Table 32.1. Timer Settings for Standard Baud Rates
Using The Internal 24.5 MHz Oscillator .............................................. 261
Table 32.2. Timer Settings for Standard Baud Rates
Using an External 22.1184 MHz Oscillator ......................................... 261
Table 34.1. PCA Timebase Input Options ............................................................. 285
Table 34.2. PCA0CPM and PCA0PWM Bit Settings for PCA Modules ................. 287
12 Rev. 1.0

12 Page





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