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PDF DS1307 Data sheet ( Hoja de datos )
| Número de pieza | DS1307 | |
| Descripción | Real-Time Clock | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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DS1307
64 x 8, Serial, I2C Real-Time Clock
GENERAL DESCRIPTION
The DS1307 serial real-time clock (RTC) is a low-
power, full binary-coded decimal (BCD) clock/calendar
plus 56 bytes of NV SRAM. Address and data are
transferred serially through an I2C, bidirectional bus.
The clock/calendar provides seconds, minutes, hours,
day, date, month, and year information. The end of
the month date is automatically adjusted for months
with fewer than 31 days, including corrections for leap
year. The clock operates in either the 24-hour or 12-
hour format with AM/PM indicator. The DS1307 has a
built-in power-sense circuit that detects power failures
and automatically switches to the backup supply.
Timekeeping operation continues while the part
operates from the backup supply.
TYPICAL OPERATING CIRCUIT
VCC
VCC
VCC RPU
RPU
CRYSTAL
BENEFITS AND FEATURES
Completely Manages All Timekeeping Functions
o Real-Time Clock Counts Seconds, Minutes,
Hours, Date of the Month, Month, Day of the
Week, and Year with Leap-Year
Compensation Valid Up to 2100
o 56-Byte, Battery-Backed, General-Purpose
RAM with Unlimited Writes
o Programmable Square-Wave Output Signal
Simple Serial Port Interfaces to Most
Microcontrollers
o I2C Serial Interface
Low Power Operation Extends Battery Backup
Run Time
o Consumes Less than 500nA in Battery-
Backup Mode with Oscillator Running
o Automatic Power-Fail Detect and Switch
Circuitry
8-Pin DIP and 8-Pin SO Minimizes Required
Space
CPU
RPU = tr/Cb
X1 X2
VCC
SCL
SQW/OUT
DS1307
SDA
GND
VBAT
ORDERING INFORMATION
Optional Industrial Temperature Range: -40°C to
+85°C Supports Operation in a Wide Range of
Applications
Underwriters Laboratories® (UL) Recognized
PIN CONFIGURATIONS
TOP VLEW
X1 VCC X1
X2 SQW/OUT X2
VBAT
SCL
VBAT
GND
SDA
GND
VCC
SQW/OUT
SCL
SDA
SO (150 mils)
PDIP (300 mils)
PART
TEMP RANGE VOLTAGE (V) PIN-PACKAGE
TOP MARK*
DS1307+
DS1307N+
DS1307Z+
DS1307ZN+
DS1307Z+T&R
DS1307ZN+T&R
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
5.0 8 PDIP (300 mils)
DS1307
5.0 8 PDIP (300 mils)
DS1307N
5.0 8 SO (150 mils)
DS1307
5.0 8 SO (150 mils)
DS1307N
5.0 8 SO (150 mils) Tape and Reel DS1307
5.0 8 SO (150 mils) Tape and Reel DS1307N
+Denotes a lead-free/RoHS-compliant package.
*A “+” anywhere on the top mark indicates a lead-free package. An “N” anywhere on the top mark indicates an industrial temperature range device.
Underwriters Laboratories, Inc. is a registered certification mark of Underwriters Laboratories, Inc.
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REV: 3/15
1 page  
TYPICAL OPERATING CHARACTERISTICS
(VCC = 5.0V, TA = +25°C, unless otherwise noted.)
120
110
100
90
80
70
60
50
40
30
20
10
0
1.0
ICCS vs. VCC
2.0 3.V0CC (V) 4.0
VBAT=3.0V
5.0
400
350
300
250
200
150
100
2.0
DS1307 64 x 8, Serial, I2C Real-Time Clock
IBAT vs. VBAT
VCC = 0V
SQW=32kHz
SQW off
2.5 VBACKUP (V) 3.0
3.5
325.0
IBAT vs. Temperature
VCC=0V, VBAT=3.0
SQW=32kHz
275.0
225.0
175.0
-40
-20
0 20 40
TEMPERATURE (°C)
60
SQW off
80
32768.5
SQW/OUT vs. Supply Voltage
32768.4
32768.3
32768.2
32768.1
32768
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Supply (V)
5 of 14
5 Page 
Figure 3. Data Transfer on I2C Serial Bus
DS1307 64 x 8, Serial, I2C Real-Time Clock
SDA
MSB
R/W
DIRECTION
BIT
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
SCL
START
CONDITION
12
678
9
ACK
1 2 3-7 8 9
ACK
REPEATED IF MORE BYTES
ARE TRANSFERED
STOP
CONDITION
OR
REPEATED
START
CONDITION
Depending upon the state of the R/W bit, two types of data transfer are possible:
1. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the
slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received
byte. Data is transferred with the most significant bit (MSB) first.
2. Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is transmitted
by the master. The slave then returns an acknowledge bit. This is followed by the slave transmitting a number
of data bytes. The master returns an acknowledge bit after all received bytes other than the last byte. At the
end of the last received byte, a “not acknowledge” is returned.
The master device generates all the serial clock pulses and the START and STOP conditions. A transfer is
ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also
the beginning of the next serial transfer, the bus will not be released. Data is transferred with the most
significant bit (MSB) first.
11 of 14
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet DS1307.PDF ] | |
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