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PDF PC1089K Data sheet ( Hoja de datos )
| Número de pieza | PC1089K | |
| Descripción | 1/3 inch NTSC/PAL CMOS Image Sensor | |
| Fabricantes | Pixelplus | |
| Logotipo |  |
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Preliminary
Customer
Data sheet
1/3 inch NTSC/PAL CMOS Image Sensor with
720 X 480 Pixel Array
PC1089K
Rev 1.1
Last update : 26. July. 2011
6th Floor, Gyeonggi R&DB Center, 906-5 Iui-dong, Yeongtong-gu,
Suwon-si, Gyeonggi-do, 443-766, Korea
Tel : 82-31-888-5300, FAX : 82-31-888-5398
Copyright ⓒ 2010, Pixelplus Co.,Ltd
ALL RIGHTS RESERVED
1 page  
PRELIMINARY
PC1089K
1/3 inch NTSC/PAL CMOS Image Sensor with
720 X 480 Pixel Array
21 DVDD
22 HVDD
33 HGND
24 DGND
25 SDA
26 SCL
27 HSYNC
28 HGND
29 D2
30 D3
31 HVDD
32 D4
33 D5
34 D6
35 D7
36 D8
37 D9
38 VSYNC
39 RSTB
40 ISIN
41 AGND
42 AVDD
43 STDBY
44 CADD1
45 CADD0
46 LED
47 TE
48 GENI
49 GENO
50 MIRS0
51 MIRS1
52 IRIS0
53 IRIS1
Digital Power supply : In case of using on-chip digital regulator, DVDD must
P be tied to DGND by total 1uF bypass capacitor. Otherwise, 1.5V DC must be
supplied with 100nF to DGND.
P Digital VDD for I/O : 3.3V. Voltage range for all output signals is (0V~HVDD)
P Digital GND for I/O
P Digital GND for core
I/O 2-wire serial interface data.
I/O 2-wire serial interface clock.
O
Horizontal synchronization pulse. HSYNC is high (or low) for the horizontal window of
interest. It can be programmed to appear or not outside the vertical window of interest.
P Digital GND for I/O
O Bit 2 of data output
O Bit 3 of data output
P Digital vdd: 3.3V for I/O. Voltage range for all output signals is (0V~HVDD)
O Bit 4 of data output
O Bit 5 of data output
O Bit 6 of data output
O Bit 7 of data output
O Bit 8 of data output
O Bit 9 of data output
O Vertical sync : Indicates the start of a new frame
I
System reset must remain low for at least 8 master clocks after power is stabilized.
When the sensor is reset, all registers are set to their default values.
I Illumination sensor input (must be under 1.0V).
P Analog Ground
P Analog VDD : 2.8V DC
I
Power stdby mode. When Stdby ='1', there's no current flow in any analog circuit branch,
neither any beat of digital clock.
I
Chip Address selection bits [1:0], Default [11]
I
O LED provides the enable signal which can turn-on LED device when low light condition
I Chip Test mode enable.
I
External Frame sync input. Slave chip can receive the external frame sync signal from
master chip
O
External Frame sync output. Master chip can output the external frame sync signal
through this pad to synchronize all digital outputs of two or more chips
O
Moving IR/AR transition Switch control PADs
O
O
IRIS control PADs
O
[Table 2] Pin Descriptions
Rev 1.1
5/145
CrystalImage & ImagingInnovation
5 Page 
PRELIMINARY
PC1089K
1/3 inch NTSC/PAL CMOS Image Sensor with
720 X 480 Pixel Array
[Fig. 9] shows the RGB444 data sequence of PC1089K. The RGB444 data sequence can change to
[x4R4, G4B4] and [G4B4, X4R4] by format (register value).
VSYNC period = frameheight + 1 [line]
VSYNC positive width = vsyncstoprow – vsyncstartrow [line]
VSYNC
HSYNC
HSYNC period = 2 x ( framewidth + 1 ) [PCLK]
HSYNC positive width = 2 x (windowx2 – windowx1 +1 ) [PCLK]
HSYNC
X1
PCLK
DATA AB *X *G *X *G *X *G
*X *G *X *G *X *G FF 00
AB U
* X : X4R4
* G : G4B4
[Fig. 9] Timing diagram for VSYNC, HSYNC, X1, PCLK and Data ( RGB444 mode )
Rev 1.1
11/145
CrystalImage & ImagingInnovation
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PC1089K.PDF ] | |
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