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54HC589 Schematic ( PDF Datasheet ) - Motorola Semiconductors

Teilenummer 54HC589
Beschreibung 8-Bit Serial or Parallel-Input/Serial-Output Shift Register
Hersteller Motorola Semiconductors
Logo Motorola Semiconductors Logo 




Gesamt 10 Seiten
54HC589 Datasheet, Funktion
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
8-Bit Serial or Parallel-Input/
Serial-Output Shift Register
with 3-State Output
High–Performance Silicon–Gate CMOS
The MC54/74HC589 is similar in function to the HC597, which is not a
3–state device. The device inputs are compatible with standard CMOS
outputs, with pullup resistors, they are compatible with LSTTL outputs.
This device consists of an 8–bit storage latch which feeds parallel data to
an 8–bit shift register. Data can also be loaded serially (see Function Table).
The shift register output, QH, is a three–state output, allowing this device to
be used in bus–oriented systems.
The HC589 directly interfaces with the Motorola SPI serial data port on
CMOS MPUs and MCUs.
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 526 FETs or 131.5 Equivalent Gates
MC54/74HC589
16
1
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
16
1
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
16
1
D SUFFIX
SOIC PACKAGE
CASE 751B–05
ORDERING INFORMATION
MC54HCXXXJ
MC74HCXXXN
MC74HCXXXD
Ceramic
Plastic
SOIC
SERIAL
DATA
INPUT
SA 14
PARALLEL
DATA
INPUTS
A 15
B1
C2
D3
E4
F5
G6
H7
LATCH CLOCK 12
SHIFT CLOCK 11
SERIAL SHIFT/
PARALLEL LOAD
OUTPUT ENABLE
13
10
LOGIC DIAGRAM
DATA
LATCH
SHIFT
REGISTER
VCC = PIN 16
GND = PIN 8
9 QH
SERIAL
DATA
OUTPUT
PIN ASSIGNMENT
B1
C2
16 VCC
15 A
D3
E4
F5
14 SA
13
SERIAL SHIFT/
PARALLEL LOAD
12 LATCH CLOCK
G6
H7
11 SHIFT CLOCK
10 OUTPUT ENABLE
GND 8
9 QH
www.DataSheet4U.com
10/95
© Motorola, Inc. 1995
3–1 REV 6






54HC589 Datasheet, Funktion
MC54/74HC589
DEVICE
UNDER
TEST
TEST CIRCUIT
TEST POINT
OUTPUT
1 k
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
* Includes all probe and jig capacitance
Figure 9.
PIN DESCRIPTIONS
DATA INPUTS
A, B, C, D, E, F, G, H (Pins 15, 1, 2, 3, 4, 5, 6, 7)
Parallel data inputs. Data on these inputs are stored in the
data latch on the rising edge of the Latch Clock input.
SA (Pin 14)
Serial data input. Data on this input is shifted into the shift
register on the rising edge of the Shift Clock input if Serial
Shift/Parallel Load is high. Data on this input is ignored when
Serial Shift/Parallel Load is low.
CONTROL INPUTS
Serial Shift/Parallel Load (Pin 13)
Shift register mode control. When a high level is applied to
this pin, the shift register is allowed to serially shift data.
When a low level is applied to this pin, the shift register ac-
cepts parallel data from the data latch.
Shift Clock (Pin 11)
Serial shift clock. A low–to–high transition on this input
shifts data on the serial data input into the shift register and
data in stage H is shifted out QH, being replaced by the data
previously stored in stage G.
Latch Clock (Pin 12)
Data latch clock. A low–to–high transition on this input
loads the parallel data on inputs A–H into the data latch.
Output Enable (Pin 10)
Active–low output enable A high level applied to this pin
forces the QH output into the high impedance state. A low
level enables the output. This control does not affect the
state of the input latch or the shift register.
OUTPUT
QH (Pin 9)
Serial data output. This pin is the output from the last stage
of the shift register. This is a 3–state output.
MOTOROLA
3–6 High–Speed CMOS Logic Data
DL129 — Rev 6

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