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PDF DLPD3V3LC Data sheet ( Hoja de datos )
| Número de pieza | DLPD3V3LC | |
| Descripción | 3.3V LOW CAPACITANCE BIDIRECTIONAL TVS | |
| Fabricantes | Diodes Incorporated | |
| Logotipo |  |
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NOT RECOMMENDED FOR NEW DESIGNS
DLPD3V3LC
3.3V LOW CAPACITANCE BIDIRECTIONAL TVS
Features
• 330 Watts Peak Pulse Power (tp = 8x20μs)
• Transient Protection for data, signal, and VCC bus to
IEC61000-4-2 level 4 (ESD)
• Low Capacitance, typ. <3 pF
• Bidirectional Configuration
• Surface Mount Package Ideally Suited for Automated Insertion
• Lead Free By Design/RoHS Compliant (Note 3)
• "Green" Device (Note 4)
Mechanical Data
• Case: SOT-26
• Case Material: Molded Plastic, “Green” Molding Compound,
Note 4. UL Flammability Classification Rating 94V-0
• Moisture Sensitivity: Level 1 per J-STD-020
• Terminal Connections: See Diagram
• Terminals: Finish - Matte Tin annealed over Copper leadframe.
Solderable per MIL-STD-202, Method 208
• Marking Information: See Page 2
• Ordering Information: See Page 2
• Weight: 0.017 grams (approximate)
Top View
Device Schematic and
Pin Out Configuration
Maximum Ratings, Total Device @TA = 25°C unless otherwise specified
Characteristic
Peak Pulse Power (Note 2)
Symbol
Ppk
Value
330
Unit
W
Thermal Characteristics
Characteristic
Thermal Resistance, Junction to Ambient (Note 5)
Operating and Storage Temperature Range
Symbol
RθJA
TJ, TSTG
Value
286
-55 to +150
Unit
°C/W
°C
Electrical Characteristics @TA = 25°C unless otherwise specified
Reverse
Standoff
Voltage
VRWM (V)
3.3
Breakdown Voltage
VBR @ IT
Min (V)
4.0
Max (V)
⎯
Test
Current
IT (mA)
1.0
Max. Reverse
Leakage
@ VRWM
(Note 7)
IR (mA)
0.11
Max. Clamping
Voltage
@ Ip = 1A
(Note 2)
VC (V)
8.0
Max. Clamping
Voltage
VC @ IPP
(Note 2)
(V)
22
Max. Peak
Pulse Current
(Note 2)
IPP (A)
15
Typical
Total
Capacitance
(Note 1)
(pF)
2.5
Notes:
1. VR = 0V, f = 1MHz as measured between pins 1 and 3.
2 . tp = 8x20μs. See figure 2.
3. No purposefully added lead.
4. Diodes Inc.'s "Green" policy can be found on our website at http://www.diodes.com/products/lead_free/index.php.
5. Device mounted on FR-4 PCB with pad layout as shown on Diodes Inc. suggested pad layout document AP02001, which can be found on our website
at http://www.diodes.com/datasheets/ap02001.pdf.
6. From pin 3 to pin 1, and/or from pin 1 to pin 3.
7. Short duration pulse test used to minimize self-heating effect.
DLPD3V3LC
Document number: DS30662 Rev. 9 - 3
1 of 4
www.diodes.com
November 2009
© Diodes Incorporated
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| PDF Descargar | [ Datasheet DLPD3V3LC.PDF ] | |
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