PDF ADS8406 Data sheet ( Hoja de datos )

Número de pieza	ADS8406
Descripción	MICRO POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER
Fabricantes	Burr-Brown Corporation
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No Preview Available ! BurrĆBrown Products from Texas Instruments ADS8406 SLAS426A – AUGUST 2004 – REVISED DECEMBER 2004 16-BIT, 1.25 MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENTIAL INPUT, MICRO POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE FEATURES • Pseudo-Bipolar, Fully Differential Input, -VREF to VREF • 16-Bit NMC at 1.25 MSPS • ±2 LSB INL Max, -1/+1.25 LSB DNL • 90 dB SNR, -95 dB THD at 100 kHz Input • Zero Latency • Internal 4.096 V Reference • High-Speed Parallel Interface • Single 5 V Analog Supply • Wide I/O Supply: 2.7 V to 5.25 V • Low Power: 155 mW at 1.25 MHz Typ • Pin Compatible With ADS8412/8402 • 48-Pin TQFP Package APPLICATIONS • DWDM • Instrumentation • High-Speed, High-Resolution, Zero Latency Data Acquisition Systems • Transducer Interface • Medical Instruments • Communications DESCRIPTION The ADS8406 is a 16-bit, 1.25 MHz A/D converter with an internal 4.096-V reference. The device in- cludes a 16-bit capacitor-based SAR A/D converter with inherent sample and hold. The ADS8406 offers a full 16-bit interface and an 8-bit option where data is read using two 8-bit read cycles. The ADS8406 has a pseudo-bipolar, fully differential input. It is available in a 48-lead TQFP package and is characterized over the industrial -40°C to 85°C temperature range. Type/Speed 18 Bit Pseudo-Diff 16 Bit Pseudo-Diff 500 kHz ADS8383 16 Bit Pseudo Bipolar, Fully Differential 14 Bit Pseudo-Diff 12 Bit Pseudo-Diff High Speed SAR Converter Family 580 kHz ADS8381 750 MHZ ADS8371 1.25 MHz 2 MHz ADS8401 ADS8405 ADS8402 ADS8406 ADS7890 (S) ADS8411 ADS8412 3 MHz ADS7891 4 MHz ADS7881 REFOUT +IN −IN REFIN + _ CDAC 4.096-V Internal Reference SAR Comparator Clock Output Latches and 3-State Drivers Conversion and Control Logic BYTE 16-/8-Bit Parallel DATA Output Bus RESET CONVST BUSY CS RD Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004, Texas Instruments Incorporated 1 page ADS8406 www.ti.com SLAS426A – AUGUST 2004 – REVISED DECEMBER 2004 TIMING CHARACTERISTICS All specifications typical at –40°C to 85°C, +VA = +VBD = 5 V (1)(2)(3) tCONV tACQ tpd1 tpd2 tw1 tsu1 tw2 tw3 tw4 th1 td1 tsu2 tw5 ten td2 td3 tw6 tw7 th2 tsu3 th3 tdis td5 tsu4 td6 td7 tsu(AB) tsu5 th4 PARAMETER Conversion time Acquisition time CONVST low to BUSY high Propagation delay time, end of conversion to BUSY low Pulse duration, CONVST low Setup time, CS low to CONVST low Pulse duration, CONVST high CONVST falling edge jitter Pulse duration, BUSY signal low Pulse duration, BUSY signal high Hold time, First data bus data transition (RD low, or CS low for read cycle, or BYTE input changes) after CONVST low Delay time, CS low to RD low (or BUSY low to RD low when CS = 0) Setup time, RD high to CS high Pulse duration, RD low time Enable time, RD low (or CS low for read cycle) to data valid Delay time, data hold from RD high Delay time, BYTE rising edge or falling edge to data valid Pulse duration, RD high Pulse duration, CS high time Hold time, last RD (or CS for read cycle ) rising edge to CONVST falling edge Setup time, BYTE transition to RD falling edge Hold time, BYTE transition to RD falling edge Disable time, RD high (CS high for read cycle) to 3-stated data bus Delay time, end of conversion to MSB data valid Byte transition setup time, from BYTE transition to next BYTE transition Delay time, CS rising edge to BUSY falling edge Delay time, BUSY falling edge to CS rising edge Setup time, from the falling edge of CONVST (used to start the valid conversion) to the next falling edge of CONVST (when CS = 0 and CONVST used to abort) or to the next falling edge of CS (when CS is used to abort) Setup time, falling edge of CONVST to read valid data (MSB) from current conversion Hold time, data (MSB) from previous conversion hold valid from falling edge of CONVST MIN 500 150 20 0 20 Min(tACQ) 40 0 0 50 0 2 20 20 50 0 0 50 50 50 60 MAX(tCONV) + MAX(td5) TYP MAX UNIT 650 ns ns 40 ns 5 ns ns ns ns 10 ps ns 610 ns ns ns ns ns 20 ns ns 20 ns ns ns ns ns ns 20 ns 10 ns ns ns ns 500 ns MIN(tCONV) ns ns (1) All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2. (2) See timing diagrams. (3) All timings are measured with 20-pF equivalent loads on all data bits and BUSY pins. 5 5 Page www.ti.com TIMING DIAGRAMS (continued) tw1 CONVST (used in normal conversion) CONVST (used in ABORT) tpd1 BUSY tsu(AB) tw4 tpd2 ADS8406 SLAS426A – AUGUST 2004 – REVISED DECEMBER 2004 tw2 tcycle tsu(AB) tpd1 tw3 CS = 0 CONVERT† SAMPLING† (When CS = 0) BYTE tCONV th1 t(ACQ) tsu4 RD Data to be read† DB[15:8] Invalid Previous Conversion th4 tsu5 Hi−Z ten Current Conversion D [15:8] D [7:0] tCONV th2 tdis Invalid Hi−Z DB[7:0] Hi−Z D [7:0] Hi−Z †Signal internal to device Figure 3. Timing for Conversion and Acquisition Cycles With CS Tied to BDGND, RD Toggling 11 11 Page

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