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R5F11BCEALA Schematic ( PDF Datasheet ) - Renesas

Teilenummer R5F11BCEALA
Beschreibung MCU
Hersteller Renesas
Logo Renesas Logo 




Gesamt 30 Seiten
R5F11BCEALA Datasheet, Funktion
RL78/G1F
RENESAS MCU
Datasheet
R01DS0246EJ0100
Rev. 1.00
Apr 06, 2015
1. OUTLINE
1.1 Features
Ultra-low power consumption technology
• VDD = single power supply voltage of 1.6 to 5.5 V which
can operate a 1.8 V device at a low voltage
• HALT mode
• STOP mode
• SNOOZE mode
RL78 CPU core
• CISC architecture with 3-stage pipeline
• Minimum instruction execution time: Can be changed
from high speed (0.03125 s: @ 32 MHz operation with
high-speed on-chip oscillator) to ultra-low speed (30.5
s: @ 32.768 kHz operation with subsystem clock)
• Multiply/divide/multiply & accumulate instructions are
supported.
• Address space: 1 MB
• General-purpose registers: (8-bit register 8) 4 banks
• On-chip RAM: 5.5 KB
Code flash memory
• Code flash memory: 32/64 KB
• Block size: 1 KB
• Prohibition of block erase and rewriting (security
function)
• On-chip debug function
• Self-programming (with boot swap function/flash shield
window function)
Data flash memory
• Data flash memory: 4 KB
• Back ground operation (BGO): Instructions can be
executed from the program memory while rewriting the
data flash memory.
• Number of rewrites: 1,000,000 times (TYP.)
• Voltage of rewrites: VDD = 1.8 to 5.5 V
High-speed on-chip oscillator
• Select from 64 MHz, 48 MHz, 32 MHz, 24 MHz, 16 MHz,
12 MHz, 8 MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz, and
1 MHz
• High accuracy: ±1.0% (VDD = 1.8 to 5.5 V, TA = -20 to
+85°C)
Operating ambient temperature
• TA = 40 to +85°C (A: Consumer applications)
• TA = 40 to +105°C (G: Industrial applications)
Power management and reset function
• On-chip power-on-reset (POR) circuit
• On-chip voltage detector (LVD) (Select interrupt and
reset from 14 levels)
Data transfer controller (DTC)
• Transfer modes: Normal transfer mode, repeat transfer
mode, block transfer mode
• Activation sources: Activated by interrupt sources.
• Chain transfer function
R01DS0246EJ0100 Rev. 1.00
Apr 06, 2015
Event link controller (ELC)
• Event signals of 22 types can be linked to the specified
peripheral function.
Serial interfaces
• CSI: 3 to 6 channels
• UART/UART (LIN-bus supported): 3 channels
• I2C/simplified I2C: 3 to 6 channels
• IrDA: 1 channel
Timer
• 16-bit timer: 9 channels
(Timer Array Unit (TAU): 4 channels, Timer RJ: 1
channel, Timer RD: 2 channels (with PWMOPA),
Timer RG: 1 channel, Timer RX: 1 channel)
• 12-bit interval timer: 1 channel
• Real-time clock: 1 channel (calendar for 99 years, alarm
function, and clock correction function)
• Watchdog timer: 1 channel (operable with the dedicated
low-speed on-chip oscillator)
A/D converter
• 8/10-bit resolution A/D converter (VDD = 1.6 to 5.5 V)
• Analog input: 8 to 17 channels
• Internal reference voltage (1.45 V) and temperature
sensor
D/A converter
• 8-bit resolution D/A converter (VDD = 1.6 to 5.5 V)
• Analog output: 1 or 2 channels
• Output voltage: 0 V to VDD
• Real-time output function
Comparator
• 2 channels (pin selector is provided for 1 channel)
<R> • Incorporates a function for the output of a timer window
in combination with the timer array unit.
• The external reference voltage or internal reference
voltage can be selected as the reference voltage.
Programmable gain amplifier (PGA)
• 1 channel
I/O port
• I/O port: 20 to 58 (N-ch open drain I/O [withstand
voltage of 6 V]: 2 to 4, N-ch open drain I/O [VDD
withstand voltage/EVDD withstand voltage]: 10 to 16)
• Can be set to N-ch open drain, TTL input buffer, and on-
chip pull-up resistor
• Different potential interface: Can connect to a 1.8/2.5/3
V device
• On-chip key interrupt function
• On-chip clock output/buzzer output controller
Others
• On-chip BCD (binary-coded decimal) correction circuit
Remark The functions mounted depend on the
product. See 1.6 Outline of Functions.
Page 1 of 140






R5F11BCEALA Datasheet, Funktion
RL78/G1F
1.3.2 32-pin products
• 32-pin plastic LQFP (7 7 mm, 0.8 mm pitch)
1. OUTLINE
P147/ANI18/IVREF0
P23/ANI3/ANO1/PGA GND
P22/ANI2/ANO0/PGA I/IVCMP0
P21/ANI1/AVREFM/IVCMP13
P20/ANI0/AVREFP/INTP11/IVCMP12
P01/ANI16/TO00/RxD1/TRG CL KB/(TRJIO0)/INTP10/IVCMP11
P00/ANI17/TI00/TxD1/TRG CL KA/(TRJO0)/INTP8/IVCMP10
P120/ANI19/VCOUT0
24 23 22 21 20 19 18 17
25 16
26 15
27 14
28 13
29 12
30 11
31 10
32 9
12345678
P51/INTP2/SO00/TxD0/TOOLTxD/TRG IO B/(TRDIOD1)
P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRG IO A/(TRJO0)/(TRDIOC1)
P30/INTP3/SCK00/SCL00/TRJO0/(TRDIOB1)
P70/INTP6/(VCOUT1)
P72/INTP7/(TxD1)
P73 / (R xD 1)/ (VC OU T0)
P74/SDAA0
P31/TI03/TO03/INTP4/PCLBUZ0/SSI00/(TRJIO0)/VCOUT1/SCLA0
Caution Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection registers 0 to 3
(PIOR0 to PIOR3).
R01DS0246EJ0100 Rev. 1.00
Apr 06, 2015
Page 6 of 140

6 Page









R5F11BCEALA pdf, datenblatt
RL78/G1F
1. OUTLINE
1.6 Outline of Functions
Caution
This outline describes the functions at the time when Peripheral I/O redirection register 0, 1
(PIOR0, 1) are set to 00H.
(1/2)
24-pin
32-pin
36-pin
48-pin
64-pin
Item
R5F11B7x
(x = C, E)
R5F11BBx
(x = C, E)
R5F11BCx
(x = C, E)
R5F11BGx
(x = C, E)
R5F11BLx
(x = C, E)
Code flash memory (KB)
32, 64
32, 64
32, 64
32, 64
32, 64
Data flash memory (KB)
44444
RAM (KB)
5.5 Note
5.5 Note
5.5 Note
5.5 Note
5.5 Note
Address space
1 MB
Main system
clock
High-speed system
clock
X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
HS (high-speed main) mode: 1 to 20 MHz (VDD = 2.7 to 5.5 V),
HS (high-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V),
LS (low-speed main) mode: 1 to 8 MHz (VDD = 1.8 to 2.7 V),
LV (low-voltage main) mode: 1 to 4 MHz (VDD = 1.6 to 1.8 V)
High-speed on-chip
oscillator clock (fIH)
HS (high-speed main) mode: 1 to 32 MHz (VDD = 2.7 to 5.5 V),
HS (high-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V),
LS (low-speed main) mode: 1 to 8 MHz (VDD = 1.8 to 5.5 V),
LV (low-voltage main) mode: 1 to 4 MHz (VDD = 1.6 to 5.5 V)
Subsystem clock
— XT1 (crystal) oscillation, external subsystem clock input
(EXCLKS) 32.768 kHz
Low-speed on-chip oscillator clock
15 kHz (TYP.): VDD = 1.6 to 5.5 V
General-purpose register
8 bits 32 registers (8 bits 8 registers 4 banks)
Minimum instruction execution time
0.03125 s (High-speed on-chip oscillator clock: fIH = 32 MHz operation)
0.05 s (High-speed system clock: fMX = 20 MHz operation)
— 30.5 s (Subsystem clock: fSUB = 32.768 kHz operation)
Instruction set
• Data transfer (8/16 bits)
• Adder and subtractor/logical operation (8/16 bits)
• Multiplication (8 bits 8 bits, 16 bits 16 bits), Division (16 bits ÷ 16 bits, 32 bits ÷ 32 bits)
• Multiplication and Accumulation (16 bits 16 bits + 32 bits)
• Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc.
I/O port
Total
20 28 31 44 58
CMOS I/O
17
(N-ch O.D. output
[VDD withstand
voltage]: 10)
25
(N-ch O.D. output
[VDD withstand
voltage]: 12)
24
(N-ch O.D. output
[VDD withstand
voltage]: 10)
34
(N-ch O.D. output
[VDD withstand
voltage]: 12)
48
(N-ch O.D. output
[VDD withstand
voltage]: 12)
CMOS input
33555
CMOS output
———
1
1
N-ch open-drain I/O (6
2
4
4
V tolerance)
Timer
16-bit timer
9 channels
(TAU: 4 channels, Timer RJ: 1 channel, Timer RD: 2 channels (with PWMOPA), Timer RX: 1 channel,
Timer RG: 1 channel)
Watchdog timer
1 channel
Real-time clock (RTC) 1 channel
12-bit interval timer
1 channel
Timer output
Timer outputs:
13 channels
PWM outputs:
8 channels
Timer outputs:
16 channels
PWM outputs:
9 channels
RTC output
1
• 1 Hz (subsystem clock: fSUB = 32.768 kHz)
Note
This is about 4.5 KB when the self-programming function and data flash function are used (For details, see CHAPTER 3
in the RL78/G1F User’s Manual).
R01DS0246EJ0100 Rev. 1.00
Apr 06, 2015
Page 12 of 140

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