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A24C64 Schematic ( PDF Datasheet ) - AiT Semiconductor

Teilenummer A24C64
Beschreibung TWO-WIRE SERIAL 64K BITS (8192 x 8) EEPROM
Hersteller AiT Semiconductor
Logo AiT Semiconductor Logo 




Gesamt 16 Seiten
A24C64 Datasheet, Funktion
AiT Semiconductor Inc.
www.ait-ic.com
A24C64
EEPROM
TWO-WIRE SERIAL 64K BITS (8192 X 8)
DESCRIPTION
FEATURES
A24C64 provides 65536 bits of serial electrically
erasable and programmable read-only memory
(EEPROM) organized as 4096 words of 8 bits each.
The A24C64 is optimized for use in many industrial
and commercial applications where low-power and
low-voltage operations are essential. The A24C64
is accessed via a two-wire serial interface.
The A24C64 is available in SOP8 and TSSOP8
packages.
Two-Wire Serial Interface
VCC=1.8V To 5.5V
Bi-Directional Data Transfer Protocol
Internal Organized 8192 x 8 (64K bits)
400KHz (1.8V, 2.7V & 5V) Compatibility
32-byte Page Write Mode
Partial Page Writes Allowed
Self-Timed Write Cycle (5ms Max)
High-Reliability
1 Million Write Cycles guaranteed
Data Retention > 100 Years
Operating Temperature: -40oC to +85oC
Available in SOP8 and TSSOP8 Package
ORDERING INFORMATION
Package Type
Part Number
A24C64M8R
SOP8
A24C64M8U
M8
A24C64M8VR
A24C64M8VU
A24C64TMX8R
TSSOP8
A24C64TMX8U
TMX8
A24C64TMX8VR
A24C64TMX8VU
Note
R: Tape & Reel
U: Tube
V: Halogen free Package
AiT provides all RoHS products
suffix “ V “ means Halogen free Package
REV1.2 - SEP 2008 Released, JAN 2012 UPDATED -
-1-






A24C64 Datasheet, Funktion
AiT Semiconductor Inc.
www.ait-ic.com
A24C64
EEPROM
TWO-WIRE SERIAL 64K BITS (8192 X 8)
DETAILED INFORMATION
Memory Organization
A24C64 64K SERIAL EEPROM: The 64K is internally organized as 256 pages of 32 bytes each. Random
word addressing requires a 13-bit data word address.
Device Operation
Clock and Data Transitions: The SDA pin is normally pulled high with an external device. Data on the SDA pin
may change only during SCL low time periods (see Figure 1 on page10). Data changes during SCL high
periods will indicate a start or stop condition as defined below.
START CONDITION
A high-to-low transition of SDA with SCL high is a start condition which must precede any other command
(see Figure 2 on page10).
STOP CONDITION
A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command
will place the EEPROM in a standby power mode (see Figure 2 on page10).
ACKNOWLEDGE
All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM
sends a “0” to acknowledge that it has received each word. This happens during the ninth clock cycle.
STANDBY MODE
The A24C64 features a low-power standby mode which is enabled: (a) upon power-up and (b) after the
receipt of the STOP bit and the completion of any internal operations.
MEMORY RESET
After an interruption in protocol, power loss or system reset, any two-wire part can be reset by following these
steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition.
REV1.2 - SEP 2008 Released, JAN 2012 UPDATED -
-6-

6 Page









A24C64 pdf, datenblatt
AiT Semiconductor Inc.
www.ait-ic.com
Figure 8 Random Read
A24C64
EEPROM
TWO-WIRE SERIAL 64K BITS (8192 X 8)
Figure 9 Sequential Read
BUS TIMING
Figure 10 SCL: Serial Clock, SDA: Serial Data I/O
REV1.2 - SEP 2008 Released, JAN 2012 UPDATED -
- 12 -

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