Datenblatt-pdf.com


A8600EJPTR-T Schematic ( PDF Datasheet ) - Allegro MicroSystems

Teilenummer A8600EJPTR-T
Beschreibung Quadruple Output Regulator
Hersteller Allegro MicroSystems
Logo Allegro MicroSystems Logo 




Gesamt 30 Seiten
A8600EJPTR-T Datasheet, Funktion
A8600
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
Features and Benefits
• Four independent, high current switching regulators
• Adjustable 1.0 A/±1.5% always-on asynchronous buck
regulator with an integrated 150 mΩ MOSFET (SW1)
Employs PFM to deliver 3.3 V/40 μA while drawing less
than 50 μA from VIN of 12 V
Operates down to at least 3.6 VIN
• Adjustable 1.5 A/±1.5% asynchronous buck regulator with
an integrated 120 mΩ high-side MOSFET (SW2)
• Adjustable 2.0 A/±1.5% asynchronous buck regulator with
an integrated 110 mΩ MOSFET (SW3)
• Adjustable ±1.5% synchronous buck controller with
integrated gate drivers and current sensing (SW4)
• Fixed 425 kHz, interleaved PWM switching frequency
• EN/SYNC input for PWM frequency scaling
• Adjustable soft-start time for each switching regulator
• All switching regulators provide prebias startup with zero
reverse current
• All switching regulators have overvoltage protection
• External compensation for all switching regulators
Continued on the next page…
Package: 48-pin LQFP (suffix JP)
Description
Designed to provide the power supply requirements of next
generation car audio and infotainment systems, the A8600
provides all the control and protection circuitry to produce
four high current regulators, each with ±1.5% accuracy. The
A8600 includes control circuitry to implement three adjustable,
asynchronous buck regulators with integrated MOSFETs. Also,
the A8600 provides the control circuitry, gate drivers, and
current sensing to implement a synchronous buck controller
with external MOSFETs. In standby mode, the A8600 draws
less than 50 μA from VIN of 12 V while employing pulse
frequency modulation (PFM) to deliver 3.3 V/40 μA via the
always-on regulator, SW1. The always-on regulator operates
down to at least VIN of 3.6 V (VIN falling).
Features of the A8600 include: an EN/SYNC input to either
turn the A8600 on/off or increase/decrease the base pulse
width modulation (PWM) frequency, four adjustable soft-start
times, and four external compensation pins. Output voltage
monitoring of switchers SW2, SW3, and SW4 is provided
by a single, open-drain POK output. In addition, the A8600
provides two high voltage, high-side switches with foldback
overcurrent protection. These two high-side switches actively
block reverse current. The A8600 also provides direct battery
(BU) and switched (accessory) battery (ACC) detectors and
a mute pulse output with an adjustable delay.
Continued on the next page…
Not to scale
A8600-DS, Rev. 3
Switcher 1
(SW1)
Adjustable
Output Voltage
1.0 AAVG / 2.5 APEAK
Always-On
PWM / PFM
Asynchronous
Buck
Regulator
Switcher 2
(SW2)
Adjustable
Output Voltage
1.5 AAVG / 2.5 APEAK
PWM
Asynchronous
Buck
Regulator
Switcher 3
(SW3)
Adjustable
Output Voltage
2.0 AAVG / 2.5 APEAK
PWM
Asynchronous
Buck
Regulator
Switcher 4
(SW4)
Adjustable
Output Voltage
Adjustable ILIM
PWM
Synchronous
Buck
Controller
Charge
Pump
Enable and
Synchronization
(EN/SYNC)
425 kHz
180° Shift
High-Side Switch 1
(S1)
1.0 Ω Total
with
Foldback Limiting
High-Side Switch 2
(S2)
1.0 Ω Total
with
Foldback Limiting
BU and ACC
Detectors
Mute Pulse
with Delay
Figure 1. A8600 major features






A8600EJPTR-T Datasheet, Funktion
A8600
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
Top Level Functional Block Diagram and Typical Application Circuit
VBAT
35 V
5.0 V
To
microcontroller
Optional: POK
to OUT2 short
protection for
microcontroller
From
microcontroller
Optional: ENS
to OUT1 for short
protection for
microcontroller
ACC
Switch
60.4 kΩ
1%
60.4 kΩ
1%
22.1 kΩ
1%
78.7 kΩ
1%
VBAT _FILT
2200 μF
A8600
CP1
27 pF
RZ1
18.7 kΩ
COMP1
SS 1
CZ1
4.7 nF
CSS1
0.68 μF VIN1
1.0 μF
C
VREG
LDO
Bias
Switch On
Off
BIAS >3.2V and
BIAS >LDO OUT
VREG
Band 1.205VREF
Gap
CP2
27 pF
CZ2
2.2 nF
CP3
27 pF
CZ3
2.2 nF
RZ2
39.2 kΩ
COMP2
SS 2
CSS2
22 nF
VREG
POR
TSDH
TSD
SQ
R
ENS
RZ3 COMP3
18.7 kΩ
SS 3
CSS3
22 nF
VIN S UVLO
TSDL
SQ
R
VREG
Oscillator
180° Shift
with
Synchronization
EN/SYNC
Delay
15 n
200 kΩ
C
POK
CP4
27 pF
CZ4
2.2 nF
RZ4
24.9 kΩ
COMP4
SS 4
CSS4
22 nF
GND
POK 2
POK 3
POK 4
ENS
200 kΩ
Optional: To
protect VINS
for Field Decay test
3A
40V
CCTMR
0.1 μF
3.70 V
+
VINS UVLO
VINS
CTMR
2 μA 2μA
A
50 kΩ
Charge
Pump
215 mV
1.205 V
825 kΩ
475 kΩ 1%
1%
1 MΩ
1%
ACCI
B
BUI
B
6.2 V
6.2 V
C
BIAS
BOOT 1
3.3 to 5.5 V
VREG POR
VIN1
Optional: To
A
COMP1
Switcher 1
150 mΩ
CBOOT1 CIN1
47 nF
maintain VBOOT1
during very
low VBAT
SS1
(SW1)
Adjustable
LSW1 10μH
LX1
CLK 0
Delay
2048n
Always-On
PWM/PFM
Asynchronous
Buck Regulator
EN/ PFM
10 Ω
DSW1
3A
40 V
FB1
C 47 kΩ
10 pF
147 kΩ
RFBA1
RFBB1
CSW1
50μF
VSW1
Adj 3.3 V
1.0 AAVG
2.5 APEAK
VREG POR
VREGPORH
VREGPORL
COMP2
SS2
CLK180
EN
TSDH
POK 2
Switcher 2
(SW2)
Adjustable
PWM
Asynchronous
Buck Regulator
BOOT2
VIN2
VIN2
120 mΩ
CBOOT2
47 nF
CIN2
VBAT _FILT
LX2 LSW2 15 μH
LX 2
10 Ω
DSW2
3A
40 V
FB2
16.2 kΩ
CSW2
50 μF
1.8 kΩ
RFBA2
RFBB2
VSW2
Adj (8V)
1.0 A AVG
2.5 A PEAK
VREG POR
COMP3
SS3
CLK0
EN
TSDH
POK 3
Switcher 3
(SW3)
Adjustable
PWM
Asynchronous
Buck Regulator
VREG POR
BOOT 3
VIN3
VBAT _FILT
VIN3
112 mΩ
CBOOT3
47 nF
CIN3
LX3
LX3
10 Ω
DSW3
3A
40 V
FB3
LSW3 10 μH
CSW3
50μF
14.7 kΩ
VSW3
Adj (3.3 V)
2. 0 AAVG
2. 5 APEAK
VIN3
4.7 kΩ
BOOT 4
RFBA3
RFBB3
CSN
CSP
CBOOT4
0.1 μF
VBAT _FILT
COMP4
SS4
CLK 180
EN
TSDH
Switcher 4
(SW4)
Adjustable
PWM
Synchronous
Buck Controller
POK 4
Shoot-
Through
Protec-
tion
TSDL
High-Side Switch 1
(S1) with
Foldback Limiting
HG4
LX 4
LG 4
FB4
D
50 kΩ
PGND
50 kΩ
LSW4
10 μH
DSW4
3A
40 V
Schottky for SW4 1.8 kΩ
may be omitted for
very low current
system only
RS
15 mΩ
CSW4
50 μF
11 kΩ
RFBA4
RFBB4
C
VSW4
Adj (5.7 V)
2.5 AAVG
4.0 APEAK
TSDL
1.0 Ω Total
High-Side Switch 2
(S2) with
Foldback Limiting
OUT1
200 kΩ 1μF
50 V
C
S 1A
LOAD 1
TSDL
SET
RST
CHARGE
DONE
1.0 Ω Total
Mute
Logic
8 to 32 μs
De-glitch BUCLEAN
PAD
OUT2
200 kΩ 1μF
50 V
MUTE
C
BIAS
ACCO
CBIAS
BUO
C
LOAD 2
S1A Optional: MUTE 5.0V
to VIN1 short
protection for
amplifier
Audio
Amplifier
15 kΩ
10 kΩ
9.1 kΩ
4.7 kΩ
BU 3.3V
To
TC7SH14F microcontroller
1 μF
BU 3.3V
TC 7S H14F
1μF
To
microcontroller
A Block active in Low IQ mode
B Current will not flow from ACCI to BUI or any VINx pin
C Current will not flow from ACCO, BUO, MUTE, BIAS, VREG, FB1, POK, or OUTx to any VINx pin
D SW4 lower FET must not cause VSW4 to decay during prebias startup
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6

6 Page









A8600EJPTR-T pdf, datenblatt
A8600
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
ELECTRICAL CHARACTERISTICS (continued) Valid at 5.5 V VINx 26 V, –40°C TA 125ºC, –40°C TJ 125ºC;
unless otherwise specified
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
SW2 (ASYNCHRONOUS BUCK REGULATOR)
Input Voltage
Input Voltage Range2
UVLO Start
UVLO Stop
UVLO Hysteresis
Voltage Regulation
VIN2
VUVLOON2
VUVLOOFF2
VUVLOHYS2
VIN2 rising
VIN2 falling
4.4 35
4.1 4.25 4.4
3.6 3.75 3.9
500
Feedback Voltage Accuracy
Output Voltage Setting Range
VFB2
VIN2 4.4 V, VFB2 = VCOMP2
788 800 812
VSW2
VSW2(typ) value is design target, see footnote 2
for min and max voltages
1.2
8.0
9.2
Output Dropout Voltage3
Internal MOSFET2
VSW(PWM)2 VIN2 = 6.0 V, ISW2 = 1 A
5.0
High-Side MOSFET On-Resistance
High-Side MOSFET Leakage1
Low-Side MOSFET On-Resistance
BOOT Regulator
RDS(on)HS2
IHS(LKG)2
RDS(on)LS2
TJ = 25ºC, IDS2 = 1.5 A
TJ < 85°C,VEN/SYNC 0.8 V, VLX2 = 0 V,
VIN2 = 16 V
TJ = 25ºC
120 140
5
5
− − 10
BOOT Voltage Enable Threshold
BOOT Voltage Enable Hysteresis
Error Amplifier
VBOOT(TH)2 VBOOT2 rising
VBOOT(HYS)2
1.85 2.10 2.30
375
Feedback Input Bias Current1
Open Loop Voltage Gain
Transconductance
Output Current
Maximum Output Voltage
Minimum Output Voltage
COMP2 Pull Down Resistance
Pulse Width Modulation (PWM)
IFB2
AVOL2
gm2
IEA2
VEAO(max)2
VEAO(min)2
RCOMP2
VCOMP2 = 1.2 V
400 mV < VFB2
0 V < VFB2 < 400 mV
VCOMP2 = 1.2 V
Fault condition
–100
52
550
275
1.3
60
750
375
±75
1.7
1
–8
65
950
475
2.1
200
PWM Ramp Offset
Minimum Controllable On-Time
Minimum Switch Off-Time
COMP2 to SW2 Current Gain
Slope Compensation
VPWMOFFSET2 VCOMP2 set for 0% duty cycle
tON(MIN)2
tOFF(MIN)2
gmPOWER2
SE2
400
80 140 180
40 95 135
3.6
300 450 600
Unit
V
V
V
mV
mV
V
V
mΩ
μA
Ω
V
mV
nA
dB
μA/V
μA/V
μA
V
mV
kΩ
mV
ns
ns
A/V
mA/μs
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
12

12 Page





SeitenGesamt 30 Seiten
PDF Download[ A8600EJPTR-T Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
A8600EJPTR-TQuadruple Output RegulatorAllegro MicroSystems
Allegro MicroSystems

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche