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PDF A7122 Data sheet ( Hoja de datos )
| Número de pieza | A7122 | |
| Descripción | 2.4GHz GFSK Transceiver | |
| Fabricantes | AMIC Technology | |
| Logotipo |  |
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Document Title
2.4GHz GFSK Transceiver
Revision History
Rev. No.
1.0
1.1
History
Transfer from AMIC. Modify ordering information.
Revise Dimensions in Package Information
A7121/A7122
2.4GHz GFSK Transceiver
Issue Date
Nov. 9th, 2005
Apr. 28th, 2006
Remark
Released
Released
Important Notice:
AMIC-COM reserves the right to make changes to its products or to discontinue any integrated circuit product or service
without notice. AMIC-COM integrated circuit products are not designed, intended, authorized, or warranted to be suitable for
use in life-support applications, devices or systems or other critical applications. Use of AMIC-COM products in such
applications is understood to be fully at the risk of the customer.
Apr. 2006, Version 1.1
AMIC Communication Corporation
1 page  
A7121/A7122
Parameter
Digital IO DC characteristics
High Level Input Voltage (VIH)
Low Level Input Voltage (VIL)
High Level Output Voltage (VOH)
Low Level Output Voltage (VOL)
Description
@IOH= -0.5mA
@IOL= 0.5mA
Minimum Typical Maximum Unit
0.8*VDD
0
VDD-0.4
0
VDD
0.2*VDD
VDD
0.4
V
V
V
V
Note:
1. Data rate= 1Mbps @1M Mode, Data rate= 3Mbps @3M Mode. A7122 operates at 1M Mode only.
2. With external RF filter that provides minimum 17dB of attenuation in the band: 30MHz ~ 2GHz and 3GHz ~12.75GHz.
Apr. 2006, Version 1.1
4 AMIC Communication Corporation
5 Page 
A7121/A7122
STATE
SPI CMD
MS0
MS1
ERSS
FP_RDY (RDY)
RX
ERSS=1
RSSI
RX
TENDCAL
Figure 7: RSSI Measurement State Timing
4. CAL State:
There are five sub-states in the CAL (Calibration) state: IFCAL (IF filter calibration), DFCAL (Data filter calibration), DEMCAL
(Demodulator calibration), RHCAL (RSSI slope calibration @RHREF) and RLCAL (RSSI slope calibration @RLREF) where
RHREF and RLREF are two internal sources for RSSI slope calibration. The following is the sub-state diagram of the CAL state.
ECAL=1
STBY
ECAL=0
CAL
IFCAL
ECAL=0
(Manual)
DFCAL
ECAL=0
(Manual)
DEMCAL
ECAL=0
(Manual)
RHCAL
ECAL=0
(Manual)
RLCAL
ECAL=0
(Auto/Manual)
Figure 8: CAL State Sub-state Diagram
Before calibration, the EXIR and EXDR bits (Mode control register bit [9:8]) must be set to 1.By setting the ECAL bit to “1” in
the STBY state, the A7121/A7122 transceiver will move into the CAL state. If ECAL command’s assertion is not in the STBY
state, the A7121/A7122 transceiver will move into the CAL state when next movement to the STBY state takes place unless it
is reset first. Two registers must be configured, the Calibration control register (I) and (II), for starting the calibration process.
The bits 4 to 8 of the Calibration control register (I) must be set first. These bits are the selection of which calibrations are
going to be executed. They may be set to all “1” to calibrate all five items. Or some of them (one or more) should be set to “1”
to calibrate one or more items. Then the command of calibration, the ECAL bit of the Calibration control register (II), must be
set to “1”. The five sub-states will do its specific calibration in turn. The first sub-state is the IFCAL sub-state that does the
intermediate frequency filter bandwidth and center frequency calibration. The second is the DFCAL that calibrates the data
Apr. 2006, Version 1.1
10 AMIC Communication Corporation
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet A7122.PDF ] | |
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