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ADN2915 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADN2915
Beschreibung Continuous Rate 6.5 Mbps to 11.3 Gbps Clock and Data Recovery IC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADN2915 Datasheet, Funktion
Data Sheet
Continuous Rate 6.5 Mbps to 11.3 Gbps Clock and
Data Recovery IC with Integrated Limiting Amp/EQ
ADN2915
FEATURES
GENERAL DESCRIPTION
Serial data input: 6.5 Mbps to 11.3 Gbps
No reference clock required
Exceeds SONET/SDH requirements for jitter
transfer/generation/tolerance
Quantizer sensitivity: 7.3 mV typical (limiting amplifier mode)
Optional limiting amplifier, equalizer, and bypass inputs
Programmable jitter transfer bandwidth to support G.8251 OTN
Programmable slice level
Sample phase adjust (5.65 Gbps or greater)
Output polarity invert
Programmable LOS threshold via I2C
I2C to access optional features
The ADN2915 provides the receiver functions of quantization,
signal level detect, and clock and data recovery for continuous
data rates from 6.5 Mbps to 11.3 Gbps. The ADN2915 automati-
cally locks to all data rates without the need for an external
reference clock or programming. ADN2915 jitter performance
exceeds all jitter specifications required by SONET/SDH, including
jitter transfer, jitter generation, and jitter tolerance.
The ADN2915 provides manual or automatic slice adjust and
manual sample phase adjusts. Additionally, the user can select a
limiting amplifier, equalizer, or bypass at the input. The equalizer
is either adaptive or can be manually set.
Loss of signal (LOS) alarm (limiting amplifier mode only)
The receiver front-end loss of signal (LOS) detector circuit
Loss of lock (LOL) indicator
indicates when the input signal level has fallen below a user-
PRBS generator/detector
Application-aware power
430 mW at 11.3 Gbps, equalizer enabled, no clock output
380 mW at 6.144 Gbps, limiting amplifier mode, no clock
output
340 mW at 622 Mbps, input bypass mode, no clock output
Power supply: 1.2 V, flexible 1.8 V to 3.3 V, and 3.3 V
4 mm × 4 mm 24-lead LFCSP
APPLICATIONS
SONET/SDH OC-1/OC-3/OC-12/OC-48/OC-192 and all
associated FEC rates
programmable threshold. The LOS detect circuit has hysteresis
to prevent chatter at the LOS output. In addition, the input
signal strength can be read through the I2C registers.
The ADN2915 also supports pseudorandom binary sequence
(PRBS) generation, bit error detection, and input data rate
readback features.
The ADN2915 is available in a compact 4 mm × 4 mm, 24-lead
chip scale package (LFCSP). All ADN2915 specifications are
defined over the ambient temperature range of −40°C to +85°C,
unless otherwise noted.
1GFC, 2GFC, 4GFC, 8GFC, 10GFC, 1GE, and 10GE
WDM transponders
Any rate regenerators/repeaters
FUNCTIONAL BLOCK DIAGRAM
SCK
SDA
LOL
REFCLKP/
REFCLKN
(OPTIONAL)
DATOUTP/
DATOUTN
CLKOUTP/
CLKOUTN
I2C_ADDR
I2C REGISTERS
FREQUENCY
ACQUISITION
AND LOCK
DETECTOR
DATA RATE
ADN2915
CML
CML
CLK
DDR
LOS
LOS
DETECT
SAMPLE
PHASE
ADJUST
FIFO
÷N ÷2
PIN
NIN
50Ω
2
50Ω
LA
BYPASS
EQ
DATA
INPUT
SAMPLER
RXD
RXCK
DOWNSAMPLER
AND LOOP
FILTER
DCO
CLOCK
I2C
I2C
PHASE
SHIFTER
VCM
VCC
FLOAT
Figure 1.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com






ADN2915 Datasheet, Funktion
ADN2915
Data Sheet
Parameter
OC-48
OC-12
OC-3
Test Conditions/Comments
600 Hz
6 kHz
100 kHz
1 MHz
20 MHz
30 Hz
300 Hz
25 kHz
250 kHz
5 MHz
30 Hz
300 Hz
6500 Hz
65 kHz
1.3 MHz
Min Typ
1528
378
16.6
0.70
0.63
193
44
19.2
0.82
0.60
50.0
24.0
14.4
0.80
0.61
Max Unit
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
1 Jitter transfer bandwidth is programmable by adjusting TRANBW[2:0] in the DPLLA register (0x10).
2 Set TRANBW[2:0] = 1 to enter OTN mode. OTN is the optical transport network as defined in ITU G.709.
3 Fibre Channel Physical Interface 4 standard, FC-P1-4, Rev 8.00, May 21, 2008.
4 Conditions of FC-P1-4, Rev 8.00, Table 27, 800-DF-EL-S apply.
5 Must have zero errors during the tests for an interval of time that is ≤10−12 BER to pass the tests.
OUTPUT AND TIMING SPECIFICATIONS
TA = TMIN to TMAX, VCC = VCCMIN to VCCMAX, VCC1 = VCC1MIN to VCC1MAX, VDD = VDDMIN to VDDMAX, VEE = 0 V, input data
pattern: PRBS 223 − 1, ac-coupled to 100 Ω differential termination load, I2C register default settings, unless otherwise noted.
Table 3.
Parameter
CML OUTPUT CHARACTERISTICS
Data Differential Output Swing
Clock Differential Output Swing
Data Differential Output Swing
Clock Differential Output Swing
Output High Voltage
Output Low Voltage
CML OUTPUT TIMING CHARACTERISTICS
Rise Time
Fall Time
Setup Time, Full Rate Clock
Hold Time, Full Rate Clock
Setup Time, DDR Clock
Hold Time, DDR clock
Test Conditions/Comments
Min
OC-192, DATA_SWING[3:0] setting = 0xC (default)
OC-192, DATA_SWING[3:0] setting = 0xF (maximum)
OC-192, DATA_SWING[3:0] setting = 0x4 (minimum)
OC-192, CLOCK_SWING[3:0] setting = 0xC (default)
OC-192, CLOCK_SWING[3:0] setting = 0xF (maximum)
OC-192, CLOCK_SWING[3:0] setting = 0x4 (minimum)
8GFC, DATA_SWING[3:0] setting = 0xC (default)
8GFC, DATA_SWING[3:0] setting = 0xF (maximum)
8GFC, DATA_SWING[3:0] setting = 0x4 (minimum
8GFC, CLOCK_SWING[3:0] setting = 0xC (default)
8GFC, CLOCK_SWING[3:0] setting = 0xF (maximum)
8GFC, CLOCK_SWING[3:0] setting = 0x4 (minimum)
VOH, dc-coupled
535
668
189
406
448
162
540
662
190
426
489
166
VCC – 0.05
VOL, dc-coupled
VCC – 0.36
20% to 80%, at OC-192, DATOUTN/DATOUTP
20% to 80%, at OC-192, CLKOUTN/CLKOUTP
20% to 80%, at 8GFC,1 DATOUTN/DATOUTP
20% to 80%, at 8GFC,1 CLKOUTN/CLKOUTP
80% to 20%, at OC-192, DATOUTN/DATOUTP
20% to 80%, at OC-192, CLKOUTN/CLKOUTP
80% to 20%, at 8GFC,1 DATOUTN/DATOUTP
20% to 80%, at 8GFC,1 CLKOUTN/CLKOUTP
tS (see Figure 2)
tH (see Figure 2)
tS (see Figure 3)
tH (see Figure 3)
Rev. 0 | Page 6 of 36
17.4
22.2
20.4
23.1
17.5
23.9
23
25
Typ
600
724
219
508
583
217
600
725
214
518
603
213
VCC −
0.025
VCC −
0.325
32.6
28.3
33.1
29.7
33
29.2
34.2
31.3
0.5
0.5
0.5
0.5
Max Unit
672 mV p-p
771 mV p-p
252 mV p-p
570 mV p-p
659 mV p-p
249 mV p-p
666 mV p-p
778 mV p-p
245 mV p-p
588 mV p-p
680 mV p-p
245 mV p-p
VCC V
VCC − V
0.29
46.5 ps
33.1 ps
44 ps
35.8 ps
49.1 ps
33.7 ps
46.8 ps
37.1 ps
UI
UI
UI
UI

6 Page









ADN2915 pdf, datenblatt
ADN2915
1k
100
ADN2915
EQUIPMENT LIMIT
SONET MASK
10
1
0.1
10
100
10
100 1k 10k 100k
JITTER FREQUENCY (Hz)
Figure 12. Jitter Tolerance: OC-12
1M
10M
ADN2915
EQUIPMENT LIMIT
SONET MASK
1
0.1
10
100 1k 10k 100k
JITTER FREQUENCY (Hz)
Figure 13. Jitter Tolerance: OC-3
1M
10M
0
–5
–10
–15
–20
–25
–30
–35
–40
1M
10M 100M
1G
10G
FREQUENCY (Hz)
Figure 14. Typical S11 Spectrum Performance
100G
5
0
–5
–10
–15
–20
–25
–30
–35
–40
–45
1k
5
0
–5
–10
–15
–20
–25
–30
–35
–40
–45
500
12
10
8
6
4
2
0
Data Sheet
SONET MASK
10k 100k
1M
FREQUENCY (Hz)
Figure 15. Jitter Transfer: OC-12
10M
SONET MASK
5k 50k 500k
FREQUENCY (Hz)
Figure 16. Jitter Transfer: OC-3
5M
DATA RATE (Gbps)
Figure 17. Sensitivities of SONET/SDH Data Rates (BER = 10−10)
Rev. 0 | Page 12 of 36

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