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DEM16217FGH-LR Schematic ( PDF Datasheet ) - Display Elektronik

Teilenummer DEM16217FGH-LR
Beschreibung LCD MODULE
Hersteller Display Elektronik
Logo Display Elektronik Logo 




Gesamt 22 Seiten
DEM16217FGH-LR Datasheet, Funktion
Display Elektronik GmbH
LCD MODULE
DEM 16217 FGH-LR
Product specification
Version : 5
14.04.2003






DEM16217FGH-LR Datasheet, Funktion
DEM 16217 FGH-LR
6.1 PCB DRAWING AND DESCRIPTION
Product Specification
Figure 3.0
DESCRIPTION:
6-1-1.The polarity of the pin L- and the pin L+:
symbol
J2,J4
J3,J5
symbol
state
Each solder-bridge
Each solder-bridge
J3,J5
Each open
------
J2, J4
------
Each open
6-1-2. The metal-bezel should be on ground when the J1 is solder-Bridge.
6-1-3.The LED resistor should be bridged when the J6 is solder-Bridge.
6-1-4.The R7 and the R8 are the LED resistor. (R7=8,2, R8=OPEN).
LED Polarity
15 Pin
16 Pin
Anode
Cathode
Cathode
Anode
Version: 5
PAGE: 4

6 Page









DEM16217FGH-LR pdf, datenblatt
DEM 16217 FGH-LR
Product Specification
Table 5.instruction table
Instruction
RS
Instruction Code
R/W DB7 DB6 DB5 DB4 DB3 DB2
DB1 DB0
Description
Execution
time
(fosc=
270kHz)
Clear
Display
00
0
0
0
0
0
0
Write “20H” to DDRAM and set
0 1 DDRAM address to “00H” from 1.53 ms
AC.
Return
Home
00 0 0 0 0 0 0
Set DDRAM address to “00H”from
1 x AC and return cursor to its original 1.53ms
position if shifted.
Entry Mode
set
0
0
0
0
0
0
0
1
I/D
SH
Assign cursor moving direction and
enable the shift of entire display.
39us
Display
Set display (D), cursor(C), and
ON/OFF 0 0
0
0 0 0 1D
C B blinking of cursor (B) on/off control
39us
Control
bit.
Cursor or
Set cursor moving and display shift
Display
00
0
0 0 1 S/C R/L X X control bit, and the direction
39us
shift without changing of DDRAM data.
Set interface data length (DL:4-
Function set 0 0
0
0 1 DL N F
X
X
bit/8-bit), numbers of display line
(N:1-line/2-line, display font type
39us
(F:0)
Set
CGRAM 0 0
address
0
1
AC5 AC4 AC3 AC2
AC1 AC0
Set CGRAM address in address
counter.
39us
Set
CGRAM 0 0
address
1
AC6 AC5 AC4 AC3 AC2
AC1 AC0
Set DDRAM address in address
counter.
39us
Read busy
flag and
address
0
1
Whether during internal operation
BF
AC6 AC5 AC4 AC3 AC2
AC1 AC0
or not can be known by reading BF.
The contents of address counter can
also be read.
0us
Write data
to RAM
1
0
D7 D6 D5 D4 D3 D2
D1
D0
Write data into internal RAM
(DDRAM/CGRAM).
43us
Read data to
RAM
1
1
D7 D6 D5 D4 D3 D2
D1
D0
Read data into internal RAM
(DDRAM/CGRAM).
43us
NOTE: when you make an MPU program with checking the busy flag (DB7), it must be necessary 1/2 Fosc for
executing the next instruction by falling E signal after the busy flag (DB7) goes to “0”.
Version: 5
10
PAGE:

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