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ADSP-BF527 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADSP-BF527
Beschreibung Blackfin Embedded Processor
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADSP-BF527 Datasheet, Funktion
Blackfin
Embedded Processor
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
FEATURES
Up to 600 MHz high performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of
programming and compiler-friendly support
Advanced debug, trace, and performance monitoring
Accepts a wide range of supply voltages for internal and I/O
operations. See Specifications on Page 28
Programmable on-chip voltage regulator (ADSP-BF523/
ADSP-BF525/ADSP-BF527 processors only)
Qualified for Automotive Applications. See Automotive
Products on Page 87
289-ball and 208-ball CSP_BGA packages
MEMORY
132K bytes of on-chip memory (See Table 1 on Page 3 for L1
and L3 memory size details)
External memory controller with glueless support for SDRAM
and asynchronous 8-bit and 16-bit memories
Flexible booting options from external flash, SPI, and TWI
memory or from host devices including SPI, TWI, and UART
Code security with Lockbox Secure Technology
one-time-programmable (OTP) memory
Memory management unit providing memory protection
PERIPHERALS
USB 2.0 high speed on-the-go (OTG) with integrated PHY
IEEE 802.3-compliant 10/100 Ethernet MAC
Parallel peripheral interface (PPI), supporting ITU-R 656
video data formats
Host DMA port (HOSTDP)
2 dual-channel, full-duplex synchronous serial ports
(SPORTs), supporting eight stereo I2S channels
12 peripheral DMAs, 2 mastered by the Ethernet MAC
2 memory-to-memory DMAs with external request lines
Event handler with 54 interrupt inputs
Serial peripheral interface (SPI) compatible port
2 UARTs with IrDA support
2-wire interface (TWI) controller
Eight 32-bit timers/counters with PWM support
32-bit up/down counter with rotary support
Real-time clock (RTC) and watchdog timer
32-bit core timer
48 general-purpose I/Os (GPIOs), with programmable
hysteresis
NAND flash controller (NFC)
Debug/JTAG interface
On-chip PLL capable of frequency multiplication
VOLTAGE REGULATOR*
WATCHDOG TIMER
JTAG TEST AND EMULATION
PERIPHERAL
ACCESS BUS
B
INTERRUPT
CONTROLLER
L1 INSTRUCTION
MEMORY
EAB 16
USB
L1 DATA
MEMORY
DMA
CONTROLLER
DCB
DEB
DMA
ACCESS
BUS
EXTERNAL PORT
FLASH, SDRAM CONTROL
BOOT
ROM
*REGULATOR ONLY AVAILABLE ON ADSP-BF523/ADSP-BF525/ADSP-BF527 PROCESSORS
OTP MEMORY
RTC
COUNTER
SPORT0
SPORT1
UART1
UART0
NFC
PPI
SPI
TIMER7-1
TIMER0
EMAC
HOST DMA
TWI
GPIO
PORT F
GPIO
PORT G
GPIO
PORT H
PORT J
Figure 1. Processor Block Diagram
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. D
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Specifications subject to change without notice. No license is granted by implication
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Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
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ADSP-BF527 Datasheet, Funktion
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
The SDRAM controller can be programmed to interface to up
to 128M bytes of SDRAM. A separate row can be open for each
SDRAM internal bank and the SDRAM controller supports up
to 4 internal SDRAM banks, improving overall performance.
The asynchronous memory controller can be programmed to
control up to four banks of devices with very flexible timing
requirements for a wide variety of devices. Each bank occupies a
1M byte segment regardless of the size of the devices used, so
that these banks are only contiguous if each is fully populated
with 1M byte of memory.
NAND Flash Controller (NFC)
The ADSP-BF52x processors provide a NAND flash controller
(NFC). NAND flash devices provide high-density, low-cost
memory. However, NAND flash devices also have long random
access times, invalid blocks, and lower reliability over device
lifetimes. Because of this, NAND flash is often used for read-
only code storage. In this case, all DSP code can be stored in
NAND flash and then transferred to a faster memory (such as
SDRAM or SRAM) before execution. Another common use of
NAND flash is for storage of multimedia files or other large data
segments. In this case, a software file system may be used to
manage reading and writing of the NAND flash device. The file
system selects memory segments for storage with the goal of
avoiding bad blocks and equally distributing memory accesses
across all address locations. Hardware features of the NFC
include:
• Support for page program, page read, and block erase of
NAND flash devices, with accesses aligned to page
boundaries.
• Error checking and correction (ECC) hardware that facili-
tates error detection and correction.
• A single 8-bit external bus interface for commands,
addresses, and data.
• Support for SLC (single level cell) NAND flash devices
unlimited in size, with page sizes of 256 and 512 bytes.
Larger page sizes can be supported in software.
• Capability of releasing external bus interface pins during
long accesses.
• Support for internal bus requests of 16 bits.
• DMA engine to transfer data between internal memory and
NAND flash device.
One-Time Programmable Memory
The processor has 64K bits of one-time programmable non-
volatile memory that can be programmed by the developer only
one time. It includes the array and logic to support read access
and programming. Additionally, its pages can be write
protected.
OTP enables developers to store both public and private data
on-chip. In addition to storing public and private key data for
applications requiring security, it also allows developers to store
completely user-definable data such as customer ID, product
ID, MAC address, etc. Hence, generic parts can be shipped,
which are then programmed and protected by the developer
within this non-volatile memory.
I/O Memory Space
The processor does not define a separate I/O space. All
resources are mapped through the flat 32-bit address space.
On-chip I/O devices have their control registers mapped into
memory-mapped registers (MMRs) at addresses near the top of
the 4G byte address space. These are separated into two smaller
blocks, one which contains the control MMRs for all core func-
tions, and the other which contains the registers needed for
setup and control of the on-chip peripherals outside of the core.
The MMRs are accessible only in supervisor mode and appear
as reserved space to on-chip peripherals.
Booting
The processor contains a small on-chip boot kernel, which con-
figures the appropriate peripheral for booting. If the processor is
configured to boot from boot ROM memory space, the proces-
sor starts executing from the on-chip boot ROM. For more
information, see Booting Modes on Page 18.
Event Handling
The event controller on the processor handles all asynchronous
and synchronous events to the processor. The processor pro-
vides event handling that supports both nesting and
prioritization. Nesting allows multiple event service routines to
be active simultaneously. Prioritization ensures that servicing of
a higher-priority event takes precedence over servicing of a
lower-priority event. The controller provides support for five
different types of events:
• Emulation — An emulation event causes the processor to
enter emulation mode, allowing command and control of
the processor via the JTAG interface.
• RESET — This event resets the processor.
• Nonmaskable Interrupt (NMI) — The NMI event can be
generated by the software watchdog timer or by the NMI
input signal to the processor. The NMI event is frequently
used as a power-down indicator to initiate an orderly shut-
down of the system.
• Exceptions — Events that occur synchronously to program
flow (in other words, the exception is taken before the
instruction is allowed to complete). Conditions such as
data alignment violations and undefined instructions cause
exceptions.
• Interrupts — Events that occur asynchronously to program
flow. They are caused by input signals, timers, and other
peripherals, as well as by an explicit software instruction.
Each event type has an associated register to hold the return
address and an associated return-from-event instruction. When
an event is triggered, the state of the processor is saved on the
supervisor stack.
The processor event controller consists of two stages, the core
event controller (CEC) and the system interrupt controller
(SIC). The core event controller works with the system interrupt
Rev. D | Page 6 of 88 | July 2013

6 Page









ADSP-BF527 pdf, datenblatt
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
TWI CONTROLLER INTERFACE
The processors include a 2-wire interface (TWI) module for
providing a simple exchange method of control data between
multiple devices. The TWI is compatible with the widely used
I2C® bus standard. The TWI module offers the capabilities of
simultaneous master and slave operation and support for both
7-bit addressing and multimedia data arbitration. The TWI
interface utilizes two pins for transferring clock (SCL) and data
(SDA) and supports the protocol at speeds up to 400k bits/sec.
The TWI interface pins are compatible with 5 V logic levels.
Additionally, the TWI module is fully compatible with serial
camera control bus (SCCB) functionality for easier control of
various CMOS camera sensor devices.
10/100 ETHERNET MAC
The ADSP-BF526 and ADSP-BF527 processors offer the capa-
bility to directly connect to a network by way of an embedded
Fast Ethernet Media Access Controller (MAC) that supports
both 10-BaseT (10M bits/sec) and 100-BaseT (100M bits/sec)
operation. The 10/100 Ethernet MAC peripheral on the proces-
sor is fully compliant to the IEEE 802.3-2002 standard and it
provides programmable features designed to minimize supervi-
sion, bus use, or message processing by the rest of the processor
system.
Some standard features are:
• Support of MII and RMII protocols for external PHYs.
• Full duplex and half duplex modes.
• Data framing and encapsulation: generation and detection
of preamble, length padding, and FCS.
• Media access management (in half-duplex operation): col-
lision and contention handling, including control of
retransmission of collision frames and of back-off timing.
• Flow control (in full-duplex operation): generation and
detection of PAUSE frames.
• Station management: generation of MDC/MDIO frames
for read-write access to PHY registers.
• Operating range for active and sleep operating modes, see
Table 58 on Page 68 and Table 59 on Page 68.
• Internal loopback from Tx to Rx.
Some advanced features are:
• Buffered crystal output to external PHY for support of a
single crystal system.
• Automatic checksum computation of IP header and IP
payload fields of Rx frames.
• Independent 32-bit descriptor-driven Rx and Tx DMA
channels.
• Frame status delivery to memory via DMA, including
frame completion semaphores, for efficient buffer queue
management in software.
• Tx DMA support for separate descriptors for MAC header
and payload to eliminate buffer copy operations.
• Convenient frame alignment modes support even 32-bit
alignment of encapsulated Rx or Tx IP packet data in mem-
ory after the 14-byte MAC header.
• Programmable Ethernet event interrupt supports any com-
bination of:
• Any selected Rx or Tx frame status conditions.
• PHY interrupt condition.
• Wake-up frame detected.
• Any selected MAC management counter(s) at half-
full.
• DMA descriptor error.
• 47 MAC management statistics counters with selectable
clear-on-read behavior and programmable interrupts on
half maximum value.
• Programmable Rx address filters, including a 64-bin
address hash table for multicast and/or unicast frames, and
programmable filter modes for broadcast, multicast, uni-
cast, control, and damaged frames.
• Advanced power management supporting unattended
transfer of Rx and Tx frames and status to/from external
memory via DMA during low power sleep mode.
• System wakeup from sleep operating mode upon magic
packet or any of four user-definable wakeup frame filters.
• Support for 802.3Q tagged VLAN frames.
• Programmable MDC clock rate and preamble suppression.
• In RMII operation, seven unused pins may be configured
as GPIO pins for other purposes.
PORTS
Because of the rich set of peripherals, the processor groups the
many peripheral signals to four ports—Port F, Port G, Port H,
and Port J. Most of the associated pins are shared by multiple
signals. The ports function as multiplexer controls.
General-Purpose I/O (GPIO)
The processor has 48 bidirectional, general-purpose I/O (GPIO)
pins allocated across three separate GPIO modules—PORTFIO,
PORTGIO, and PORTHIO, associated with Port F, Port G, and
Port H, respectively. Port J does not provide GPIO functional-
ity. Each GPIO-capable pin shares functionality with other
processor peripherals via a multiplexing scheme; however, the
GPIO functionality is the default state of the device upon
power-up. Neither GPIO output nor input drivers are active by
default.
Rev. D | Page 12 of 88 | July 2013

12 Page





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