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PDF EM78P809N Data sheet ( Hoja de datos )
| Número de pieza | EM78P809N | |
| Descripción | 8-Bit Microcontroller | |
| Fabricantes | ELAN Microelectronics | |
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EM78P809N
8-Bit
Microcontroller
Product
Specification
DOC. VERSION 1.1
ELAN MICROELECTRONICS CORP.
October 2008
1 page  
Contents
Doc. Version
0.9
1.0
1.1
Specification Revision History
Revision Description
Preliminary
Initial Version
1. Improved the contents and format of the Features
section
2. Improved Fig.5-1. Functional Block Diagram
3. Corrected Fig.5-3. Program Counter Organization
4. Modified the title of every register illustration
5. Modified the illustrations of SPIC1, SPIC2, ADOSCR,
URC1 and URC2 registers
6. Modified Sections 4.5 AD Converter, 4.6 Time base
timer and keytone generator, 4.9.3 Window mode and
4.10 Timer/Counter 3
7. Modified Fig.5-13. SPI Block Diagram, Fig.5-23 Timing
Chart of Capture Mode, Fig.5-24. Timer/Counter 4
Configuration and Table 9 Interrupt Vector.
8. Removed Sections 5.2 Recommended Operating
Conditions and 6.1 DC Electrical characteristics
(VDD=3V±5%, VSS= 0V)
9. Modified Section 6.2 AD Converter Characteristics
10. Added Section 6.3 Device Characteristics
11. Corrected Section 6.5 Timing Diagram
12. Modified Appendix A Package Type
13. Added Appendix B Packaging Configuration
14. Added Appendix C Quality Assurance and Reliability
Date
2004/03/04
2005/07/26
2008/10/30
Product Specification (V1.1) 10.30.2008
•v
5 Page 
EM78P809N
8-Bit Microcontroller
5.2 Operating Registers
Address
REGISTER
BANK 0
00 R0/ IAR
01 R1/ TCC
02 R2/ PC
03 R3/ SR
04 R4/ RSR
05 SCR
06 Port 6
07 Port 7
08 Port 8
09 Port 9
0A Reserved
0B TC4CR
0C TC4D
0D ISFR0
0E ISFR1
0F ISFR2
10
:
16 Byte
Common Register
1F
REGISTER
BANK 1
REGISTER
BANK 2
REGISTER
BANK 3
R3 (7,6)= (0,1)
R3 (7,6)= (1,0)
R3 (7,6)= (1,1)
TC3CR
TC3DA
TC3DB
TC2CR/ ADDL
TC2DH
TC2DL
ADCR
ADIC
ADDH
TBKTC
Reserved
URC1
URC2
URS
URRD
URTD
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SPIC1
SPIC2
SPID
Reserved
Reserved
PHC1
PLC1
PHC2
PLC2
Reserved
Reserved
20
Bank 0
R4 (7,6) = (0,0)
:
3F
32 Byte
Common Register
Bank 1
R4 (7,6) = (0,1)
32 Byte
Common Register
Bank 2
R4 (7,6) = (1,0)
32 Bytes
Common Register
Bank 3
R4 (7,6) = (1,1)
32 Bytes
Common Register
Fig. 5-2 Operating Registers
CONTROL
REGISTER
Reserved
IOC6
IOC7
IOC8
IOC9
Reserved
INTCR
ADOSCR
Reserved
IMR1
IMR2
Product Specification (V1.1) 10.30.2009
(This specification is subject to change without further notice)
•5
11 Page | ||
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