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EM78P141 Schematic ( PDF Datasheet ) - ELAN Microelectronics

Teilenummer EM78P141
Beschreibung 8-Bit Microprocessor
Hersteller ELAN Microelectronics
Logo ELAN Microelectronics Logo 




Gesamt 30 Seiten
EM78P141 Datasheet, Funktion
EM78P141
8-Bit Microprocessor
with OTP ROM
Product
Specification
DOC. VERSION 1.1
ELAN MICROELECTRONICS CORP.
December 2009






EM78P141 Datasheet, Funktion
Contents
APPENDIX
A Package Type............................................................................................... 80
B Packaging Configuration ............................................................................ 80
C How to Use the ICE 143 for EM78P141 ...................................................... 81
C-1 Code Option Pin Selection with JP1 & JP2 ...................................................... 81
C-2 DIP Switch (S1 & S2) Setting........................................................................... 82
C-3 ICE 143 ICE Cable Connector (JP3) Pin Assignment....................................... 83
C-4 ICE 143 ICE Cable to Target Pin Assignment................................................... 84
Specification Revision History
Doc. Version
0.9
1.0
1.1
Revision Description
Preliminary version
Initial released version
1. Added EM78P141MS10J/S package type.
2. Modified Section 6.5.1.3 Register Initial Values After
Reset.
3. Delete IOCB0 and IOCC0 registers.
4. Modified Absolute Maximum Ratings.
Date
2008/10/25
2009/03/12
2009/12/16
vi Product Specification (V1.1) 12. 16.2009

6 Page









EM78P141 pdf, datenblatt
EM78P141
8-Bit Microprocessor with OTP ROM
6.1.3.1 Data Memory Configuration
Address
R PAGE registers
IOCX0 PAGE Registers
IOCX1 PAGE registers
00 R0 (Indirect Addressing Register)
Reserve
Reserve
01 R1 (Time Clock Counter)
Reserve
Reserve
02 R2 (ProgramCounter)
Reserve
Reserve
03 R3 (Status Register)
Reserve
Reserve
04 R4 (RAMSelect Register)
Reserve
Reserve
05 R5 (Port 5)
IOC50 (I/OPort Control Register)
IOC51
(PWMCON : PWMControl
Register)
06 R6 (LVD Control Register)
IOC60 (Pull-high Control Register)
IOC61
(TMRCON : Timer
Register)
Control
07 R7 (MCSR)
IOC70 (Pull-down Control Register)
IOC71
(PRD1 : PWM1 Time
Period)
08
R8 (ADC Input Select Register
IOC80
(Open-drain
Register)
Control
IOC81
(PRD2 : PWM2 Time
Period)
09 R9 (ADC Control Register)
IOC90 (Comparator Control
Register)
IOC91 (DT1 : PWM1 Duty Cycle)
0A
RA
(ADC Offset Calibration
Register)
IOCA0 Reserve
IOCA1 (DT2 : PWM2 Duty Cycle)
0B RB (The converted value
IOCB0 Reserve
Bit 9~Bit 2 of ADDATAH)
IOCB1 (TMR1 : PMW1 Timer)
0C RC (The converted value
Bit 1~Bit 0 of ADDATAL)
0D
RD
(THLP: LSB of Table
Point Register)
IOCC0 Reserve
IOCD0
(Code Option
Register)
Control
IOCC1 (TMR2 : PWM2 Timer)
IOCD1 (Wake-up Control Register)
0E
RE
(TBHP: MSB of Table Point
Register)
IOCE0 (Code Option Control
Register)
IOCE1 (WDT Control Register)
0F RF (Interrupt Status Register) IOCF0 (Interrupt Mask Register 1)
Reserve
10
: General Registers
1F
20
: General Registers
3F
6.1.4 R3 (Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RST
IOCS
-
T
P
Z DC C
Bit 7 (RST): Bit of reset type
Set to “1” if wake-up from Sleep mode on pin change, comparator status
change, or AD conversion completed. Set to “0” if wake-up from other
reset types.
Bit 6 (IOCS): Select the Segment of IO control register
0: Segment 0 (IOC50 ~ IOCF0) selected
1: Segment 1 (IOC51 ~ IOCF1) selected
6 Product Specification (V1.1) 12. 16.2009
(This specification is subject to change without further notice)

12 Page





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