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PDF GAL6002 Data sheet ( Hoja de datos )
| Número de pieza | GAL6002 | |
| Descripción | High Performance E2CMOS FPLA Generic Array Logic | |
| Fabricantes | Lattice Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de GAL6002 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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GAL6002
High Performance E2CMOS FPLA
Generic Array Logic™
Features
Functional Block Diagram
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— 15ns Maximum Propagation Delay
— 75MHz Maximum Frequency
— 6.5ns Maximum Clock to Output Delay
— TTL Compatible 16mA Outputs
— UltraMOS® Advanced CMOS Technology
• ACTIVE PULL-UPS ON ALL PINS
INPUT
CLOCK
{INPUTS
2-11
ICLK
2
11
ILMC
AND
OUTPUT
ENABLE
14
23
IOLMC
• LOW POWER CMOS
— 90mA Typical Icc
• E2 CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• UNPRECEDENTED FUNCTIONAL DENSITY
— 78 x 64 x 36 FPLA Architecture
— 10 Output Logic Macrocells
— 8 Buried Logic Macrocells
— 20 Input and I/O Logic Macrocells
• HIGH-LEVEL DESIGN FLEXIBILITY
— Asynchronous or Synchronous Clocking
— Separate State Register and Input Clock Pins
— Functional Superset of Existing 24-pin PAL®
and FPLA Devices
• APPLICATIONS INCLUDE:
— Sequencers
— State Machine Control
— Multiple PLD Device Integration
Description
0
7
BLMC
D
E
OR
Macrocell Names
14
D 23
OLMC
E
OCLK
ILMC INPUT LOGIC MACROCELL
IOLMC I/O LOGIC MACROCELL
BLMC BURIED LOGIC MACROCELL
OLMC OUTPUT LOGIC MACROCELL
{ OUTPUTS
14 - 23
OUTPUT
CLOCK
PinNames
I0 - I10
ICLK
OCLK
INPUT
INPUT CLOCK
OUTPUT CLOCK
I/O/Q
V
CC
GND
BIDIRECTIONAL
POWER (+5V)
GROUND
Having an FPLA architecture, the GAL6002 provides superior
flexibility in state-machine design. The GAL6002 offers the highest
degree of functional integration, flexibility, and speed currently
available in a 24-pin, 300-mil package. E2CMOS technology offers
high speed (<100ms) erase times, providing the ability to reprogram
or reconfigure the device quickly and efficiently.
The GAL6002 has 10 programmable Output Logic Macrocells
(OLMC) and 8 programmable Buried Logic Macrocells (BLMC). In
addition, there are 10 Input Logic Macrocells (ILMC) and 10
I/O Logic Macrocells (IOLMC). Two clock inputs are provided for
independent control of the input and output macrocells.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacturing. As a result, Lattice
Semiconductor delivers 100% field programmability and
functionality of all GAL products. In addition, 100 erase/write cycles
and data retention in excess of 20 years are specified.
Pin Configuration
PLCC
4
I5
2 28 26
25 I/O/Q
I I/O/Q
I7
23 I/O/Q
NC GAL6002 NC
I 9 Top View 21 I/O/Q
I I/O/Q
I 11
19 I/O/Q
12 14 16 18
DIP
I/ICLK 1
I
24 Vcc
I/O/Q
I
I GAL
I 6002
I/O/Q
I/O/Q
I/O/Q
I6
I/O/Q
I 18 I/O/Q
I I/O/Q
I I/O/Q
I I/O/Q
I I/O/Q
GND 12
13 OCLK
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
July 1997
6002_02
1
1 page  
OLMC and BLMC Configurations
OLMC ONLY
XORD(i)
D
MUX
Vcc 0
XORE(i)
E1
CKS(i)
MUX
0
1
RESET
R
D
Q
E
Specifications GAL6002
OE
PRODUCT
TERM
AND
ARRAY
IOLMC
MUX
1
0
OSYN(i)
I/O
OLMC ONLY
OC LK
OLMC/BLMC
Generic Logic Block Diagram
OLMC JEDEC Fuse Numbers
OLMC
0
1
2
3
4
5
6
7
8
9
CKS
8178
8182
8186
8190
8194
8198
8202
8206
8210
8214
OUTSYNC
8179
8183
8187
8191
8195
8199
8203
8207
8211
8215
XORE
8180
8184
8188
8192
8196
8200
8204
8208
8212
8216
XORD
8181
8185
8189
8193
8197
8201
8205
8209
8213
8217
BLMC JEDEC Fuse Numbers
BLMC
7
6
5
4
3
2
1
0
CKS
8175
8172
8169
8166
8163
8160
8157
8154
OUTSYNC
8176
8173
8170
8167
8164
8161
8158
8155
XORE
8177
8174
8171
8168
8165
8162
8159
8156
5
5 Page 
Switching Waveforms
INPUT or
I/O FEEDBACK
COMBINATORIAL
OUTPUT
VALID INPUT
tpd1,2
Combinatorial Output
INPUT or
I/O FEEDBACK
ICLK (LATCH)
COMBINATORIAL
OUTPUT
VALID INPUT
tsu1 th1
tpd3
Latched Input
tco1
INPUT or
I/O FEEDBACK
Sum Term CLK
REGISTERED
OUTPUT
VALID INPUT
tsu4 th4
tco4
1/ fmax2
Registered Output (Sum Term CLK)
INPUT or
I/O FEEDBACK
OUTPUT
tdis ten
Input or I/O to Output Enable/Disable
ICLK or
OCLK
Sum Term CLK
twh1,2
twl1,2
twh3
twl3
Clock Width
Specifications GAL6002
INPUT or
I/O FEEDBACK
ICLK (REGISTER)
COMBINATORIAL
OUTPUT
OCLK
Sum Term CLK
VALID INPUT
tsu2 th2
tco2
tsu5
tsu6
Registered Input
INPUT or
I/O FEEDBACK
OCLK
REGISTERED
OUTPUT
VALID INPUT
tsu3 th3
tco3
1/ fmax1
Registered Output (OCLK)
INPUT or
I/O FEEDBACK
DRIVING AR
REGISTERED
OUTPUT
Sum Term CLK
OCLK
tarw
tar
tarr2
tarr1
Asynchronous Reset
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet GAL6002.PDF ] | |
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