PDF GAL6001B-30LJ Data sheet ( Hoja de datos )

Número de pieza	GAL6001B-30LJ
Descripción	High Performance E2CMOS FPLA Generic Array Logic
Fabricantes	Lattice Semiconductor
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GAL6001 High Performance E2CMOS FPLA Generic Array Logic™ Features Functional Block Diagram • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — 30ns Maximum Propagation Delay — 27MHz Maximum Frequency — 12ns Maximum Clock to Output Delay — TTL Compatible 16mA Outputs — UltraMOS® Advanced CMOS Technology • LOW POWER CMOS — 90mA Typical Icc INPUT CLOCK {INPUTS 2-11 ICLK 2 11 ILMC AND OUTPUT ENABLE 14 23 IOLMC • E2 CELL TECHNOLOGY — Reconfigurable Logic — Reprogrammable Cells — 100% Tested/100% Yields — High Speed Electrical Erasure (<100ms) — 20 Year Data Retention • UNPRECEDENTED FUNCTIONAL DENSITY — 78 x 64 x 36 FPLA Architecture — 10 Output Logic Macrocells — 8 Buried Logic Macrocells — 20 Input and I/O Logic Macrocells • HIGH-LEVEL DESIGN FLEXIBILITY — Asynchronous or Synchronous Clocking — Separate State Register and Input Clock Pins — Functional Superset of Existing 24-pin PAL® and FPLA Devices 0 7 BLMC D E OR 14 D 23 OLMC E OCLK Macrocell Names ILMC INPUT LOGIC MACROCELL IOLMC I/O LOGIC MACROCELL BLMC BURIED LOGIC MACROCELL OLMC OUTPUT LOGIC MACROCELL { OUTPUTS 14 - 23 OUTPUT CLOCK • APPLICATIONS INCLUDE: — Sequencers — State Machine Control — Multiple PLD Device Integration Description Using a high performance E2CMOS technology, Lattice Semiconductor has produced a next-generation programmable logic device, the GAL6001. Having an FPLA architecture, known for its superior flexibility in state-machine design, the GAL6001 offers a high degree of functional integration and flexibility in a 24- pin, 300-mil package. The GAL6001 has 10 programmable Output Logic Macrocells (OLMC) and 8 programmable Buried Logic Macrocells (BLMC). In addition, there are 10 Input Logic Macrocells (ILMC) and 10 I/O Logic Macrocells (IOLMC). Two clock inputs are provided for independent control of the input and output macrocells. Advanced features that simplify programming and reduce test time, coupled with E2CMOS reprogrammable cells, enable 100% AC, DC, programmability, and functionality testing of each GAL6001 during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified. Pin Names I0 - I10 ICLK OCLK INPUT INPUT CLOCK OUTPUT CLOCK I/O/Q VCC GND BIDIRECTIONAL POWER (+5) GROUND Pin Configuration PLCC 4 I5 I I7 NC I9 I I 11 12 2 28 26 25 I/O/Q GAL6001 Top View I/O/Q 23 I/O/Q NC 21 I/O/Q I/O/Q 19 I/O/Q 14 16 18 DIP I/ICLK 1 I 24 Vcc I/O/Q I I/O/Q I GAL I I 6 6001 I/O/Q I/O/Q I/O/Q I 18 I/O/Q I I/O/Q I I/O/Q I I/O/Q I I/O/Q GND 12 13 OCLK Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com July 1997 6001_02 1 1 page OLMC and BLMC Configurations OLMC ONLY XORD(i) D MUX Vcc 0 XORE(i) E1 CKS(i) MUX 0 1 RESET R D Q E Specifications GAL6001 OE PRODUCT TERM AND ARRAY IOLMC MUX 1 0 OSYN(i) I/O OLMC ONLY OC LK OLMC/BLMC Generic Logic Block Diagram OLMC (Output Logic Macrocell) JEDEC Fuse Numbers BLMC (Buried Logic Macrocell) JEDEC Fuse Numbers OLMC 0 1 2 3 4 5 6 7 8 9 OCLK 8178 8182 8186 8190 8194 8198 8202 8206 8210 8214 OSYN 8179 8183 8187 8191 8195 8199 8203 8207 8211 8215 XORE 8180 8184 8188 8192 8196 8200 8204 8208 8212 8216 XORD 8181 8185 8189 8193 8197 8201 8205 8209 8213 8217 BLMC 7 6 5 4 3 2 1 0 OCLK 8175 8172 8169 8166 8163 8160 8157 8154 OSYN 8176 8173 8170 8167 8164 8161 8158 8155 XORE 8177 8174 8171 8168 8165 8162 8159 8156 5 5 Page fmax Descriptions CLK Specifications GAL6001 LOGIC ARRAY REGISTER tsu tco fmax with External Feedback 1/(tsu+tco) Note: fmax with external feedback is calculated from measured tsu and tco. CLK LOGIC ARRAY REGISTER fmax with No Feedback Note: fmax with no feedback may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. Switching Test Conditions Input Pulse Levels Input Rise and Fall Times Input Timing Reference Levels Output Timing Reference Levels Output Load GND to 3.0V 3ns 10% – 90% 1.5V 1.5V See Figure 3-state levels are measured 0.5V from steady-state active level. Output Load Conditions (see figure) Test Condition R1 R2 A B Active High Active Low C Active High Active Low 300Ω ∞ 300Ω ∞ 300Ω 390Ω 390Ω 390Ω 390Ω 390Ω CL 50pF 50pF 50pF 5pF 5pF LOGIC ARRAY CLK REGISTER t cf t pd fmax with Internal Feedback 1/(tsu+tcf) Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. For example, the timing from clock to a combinatorial output is equal to tcf + tpd. +5V R1 FROM OUTPUT (O/Q) UNDER TEST R2 TEST POINT C L* *C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE 11 11 Page

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