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PDF ADIS16133 Data sheet ( Hoja de datos )
| Número de pieza | ADIS16133 | |
| Descripción | Precision Angular Rate Sensor | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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±1200°/sec
Precision Angular Rate Sensor
ADIS16133
FEATURES
Digital gyroscope system, ±1200°/sec measurement range
In-run bias stability, ~6°/hour
~11°/hour over temperature: −40°C to +85°C
Autonomous operation and data collection
No external configuration commands required
Start-up time: 181 ms
Sleep mode recovery: 4.7 ms
Factory calibrated sensitivity and bias
Calibration temperature range: −40°C to +85°C
Single serial peripheral interface, SPI compatible
Wide bandwidth: 335 Hz
Embedded temperature sensor
Programmable operation and control
Automatic and manual bias correction controls
Digital filters: Bartlett FIR, average/decimation
Internal sample rate: up to 2048 SPS
Digital I/O: data ready, alarm indicator, general-purpose
Alarms for condition monitoring
Sleep mode for power management
Enable external sample clock input: up to 2048 Hz
Single-supply operation: 4.85 V to 5.15 V
2000 g shock survivability
Operating temperature range: −40°C to +105°C
APPLICATIONS
Precision instrumentation
Platform stabilization and control
Industrial vehicle navigation
Downhole instrumentation
Robotics
GENERAL DESCRIPTION
The ADIS16133 iSensor® is a high performance, digital gyro-
scope sensing system that operates autonomously and requires
no user configuration to produce accurate rate sensing data.
Key performance advantages include low noise density, wide
bandwidth, low variation over temperature, and excellent in-run
bias stability, all of which directly influence critical end perfor-
mance goals for platform stabilization, navigation, robotics,
and medical instrumentation systems.
This sensor system combines industry leading iMEMS® technology
with signal conditioning that optimizes dynamic performance. The
factory calibration characterizes the entire sensor signal chain for
sensitivity and bias over a temperature range of −40°C to +85°C.
As a result, each ADIS16133 has its own unique correction for-
mulas to produce accurate measurements upon installation. For
some systems, the factory calibration eliminates the need for
system level calibration and greatly simplifies it for others.
The ADIS16133 samples data at rates of up to 2048 SPS and
offers an averaging/decimation filter structure for optimizing
noise/bandwidth trade-offs. The serial peripheral interface (SPI)
and user register structure provide easy access to configuration
controls and calibrated sensor data for embedded processor
platforms.
The 36 mm × 44 mm × 14 mm package provides four holes for
simple mechanical attachment. Use M2 (or 2-56 standard size)
machine screws along with a standard 24-pin, dual row, 1 mm
pitch connector to support electrical attachment to a printed
circuit board (PCB) or cable system. The ADIS16133 provides
an operating temperature range of −40°C to +105°C.
FUNCTIONAL BLOCK DIAGRAM
DIO1 DIO2 CLKIN RST
VCC
SELF-TEST
I/O
ALARMS
POWER
MANAGEMENT
GND
MEMS
SENSOR
TEMP
SENSOR
ADIS16133
CONTROLLER
CLOCK CALIBRATION
FILTER
USER
CONTROL
REGISTERS
OUTPUT
DATA
REGISTERS
SPI
PORT
CS
SCLK
DIN
DOUT
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
1 page  
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Acceleration
Any Axis, Unpowered
Any Axis, Powered
VCC to GND
Digital Input Voltage to GND
Digital Output Voltage to GND
Operating Temperature Range
Storage Temperature Range
Rating
2000 g
2000 g
−0.3 V to +7.0 V
−0.3 V to +5.3 V
−0.3 V to VCC + 0.3 V
−40°C to +105°C
−65°C to +125°C1, 2
1 Extended exposure to temperatures outside the specified temperature
range of −40°C to +105°C can adversely affect the accuracy of the factory
calibration. For best accuracy, store the parts within the specified operating
range of −40°C to +105°C.
2 Although the device is capable of withstanding short-term exposure to
150°C, long-term exposure threatens internal mechanical integrity.
ADIS16133
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 4. Package Characteristics
Package Type
θJA
24-Lead Module (ML-24-3) 15.7°C/W
θJC
1.48°C/W
Device
Weight
25 g
ESD CAUTION
Rev. 0 | Page 5 of 20
5 Page 
DIGITAL PROCESSING CONFIGURATION
Figure 18 provides a block diagram for the sampling and digital
filter stages inside the ADIS16133. Table 15 provides a summary
of digital processing registers for sample rate and filter control.
Table 15. Digital Processing Registers
Register Name Address Description
SMPL_PRD 0x1E Sample rate control
AVG_CNT
0x20 Digital filtering and range control
DEC_RATE
0x22 Decimation rate setting
Internal Sample Rate
The SMPL_PRD register in Table 16 provides a programmable
control for the internal sample rate. Use the following formula
to calculate the decimal number for the code to write into this
register:
SMPL _
PRD
=
32,768
fS
− 1;
fS
≤
2048 SPS
The factory default setting for SMPL_PRD sets the internal
sample rate to a rate of 1024 SPS; the minimum setting for the
SMPL_PRD register is 0x000F, which results in an internal
sample rate of 2048 SPS.
Table 16. SMPL_PRD Bit Descriptions
Bits Description (Default = 0x001F)
[15:0] Clock setting bits; sets fS in Figure 18
Input Clock Configuration
Set SMPL_PRD = 0x0000 (DIN = 0x9F00, then DIN = 0x9E00)
to disable the internal clock and enable CLKIN as a clock input pin.
Digital Filtering
The AVG_CNT register (see Table 17) provides user controls
for the low-pass filter. This filter contains two cascaded averaging
filters that provide a Bartlett window FIR filter response (see
Figure 17). For example, set AVG_CNT[7:0] = 0x04 (DIN =
0xA004) to set each stage to 16 taps. When used with the
default sample rate of 1024 SPS, this establishes a −3 dB
bandwidth of approximately 20 Hz for this filter.
ADIS16133
0
–20
–40
–60
–80
–100
–120
–140
0.001
N=2
N=4
N = 16
N = 64
0.01 0.1
FREQUENCY (f/fS)
1
Figure 17. Bartlett Window FIR Filter Frequency Response
(Phase Delay = N Samples)
Table 17. AVG_CNT Bit Descriptions
Bits Description (Default = 0x0000)
[15:3] Don’t care
[2:0] Binary; B variable in Figure 18; maximum setting =
110 (binary) = 6 (decimal)
Averaging/Decimation Filter
The DEC_RATE register (see Table 18) provides user control
for the final filter stage (see Figure 18), which averages and
decimates the output data. For systems that value lower sample
rates, this filter stage provides an opportunity to lower the sample
rate while maintaining optimal bias stability performance. The
−3 dB bandwidth of this filter stage is approximately one half
the output data rate. For example, set DEC_RATE[7:0] = 0x04
(DIN = 0xA204) to reduce the sample rate by a factor of 16.
When the factory default 1024 SPS sample rate is used, this
decimation setting reduces the output data rate to 64 SPS and
the sensor bandwidth to approximately 31 Hz.
Table 18. DEC_RATE Bit Descriptions
Bits Description (Default = 0x0000)
[15:5] Don’t care
[4:0] Binary; D variable in Figure 18; maximum setting =
1000 (binary) = 16 (decimal)
MEMS
GYRO
402Hz
819Hz
÷ND
–3dB BANDWIDTH = 335Hz
fS =
32,768
SP + 1
SP ≥ 15
SP = SMPL_PRD
CLOCK
fS
CLKIN
B = AVG_CNT[2:0]
NB = 2B
NB = NUMBER OF TAPS PER STAGE
D = DEC_RATE[4:0]
ND = 2D
ND = NUMBER OF TAPS
ND = DATA RATE DIVISOR
Figure 18. Sampling and Frequency Response Block Diagram
Rev. 0 | Page 11 of 20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet ADIS16133.PDF ] | |
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