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Teilenummer | STM32F479IG |
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Beschreibung | ARM 32-bit Cortex-M4 CPU + FPU | |
Hersteller | STMicroelectronics | |
Logo | ||
Gesamt 30 Seiten STM32F479xx
ARM®Cortex®-M4 32b MCU+FPU, 225DMIPS, up to 2MB Flash/384+4KB RAM, USB, OTG
HS/FS, Ethernet, FMC, QuadSPI, Crypto, Graphical accelerator, Camera, LCD-TFT & MIPI DSI
Data brief - target specification
Features
• Core: ARM® 32-bit Cortex®-M4 CPU with FPU,
Adaptive real-time accelerator (ART
Accelerator™) allowing 0-wait state execution
from Flash memory, frequency up to 180 MHz,
MPU, 225 DMIPS/1.25 DMIPS/MHz
(Dhrystone 2.1), and DSP instructions
• Memories
– Up to 2 MB of Flash memory organized into two
banks allowing read-while-write
– Up to 384+4 KB of SRAM including 64-KB of
CCM (core coupled memory) data RAM
– Flexible external memory controller with up to
32-bit data bus: RAM,PSRAM,SDRAM/LPSDR
SDRAM, Flash NOR/NAND memories
– Dual-flash mode Quad SPI interface
• Graphics:
– Chrom-ART Accelerator™ (DMA2D), graphical
hardware accelerator enabling enhanced
graphical user interface with minimum CPU load
– LCD TFT controller supporting up to XGA
– MreIsPoIl®utDioSnI host controller supporting up to 720p
30Hz resolution
• Clock, reset and supply management
– 1.7 V to 3.6 V application supply and I/Os
– POR, PDR, PVD and BOR
– 4-to-26 MHz crystal oscillator
– Internal 16 MHz factory-trimmed RC (1%
accuracy)
– 32 kHz oscillator for RTC with calibration
– Internal 32 kHz RC with calibration
• Low power
– Sleep, Stop and Standby modes
–
V+BoApTtisounpapl l4y
for
KB
RTC, 20×32 bit
backup SRAM
backup
registers
• 3×12-bit, 2.4 MSPS ADC: up to 24 channels
and 7.2 MSPS in triple interleaved mode
• 2×12-bit D/A converters
• General-purpose DMA: 16-stream DMA
controller with FIFOs and burst support
• Up to 17 timers: up to twelve 16-bit and two 32-
bit timers up to 180 MHz, each with up to 4
IC/OC/PWM or pulse counter and quadrature
(incremental) encoder input. 2x watchdogs and
SysTick timer
• Debug mode
&"'!
LQFP176 (24 × 24 mm) UFBGA169 (7 × 7 mm) WLCSP168
LQFP208 (28 x 28 mm) TFBGA216 (13 x 13 mm)
– SWD & JTAG interfaces
– Cortex-M4 Trace Macrocell™
• Up to 161 I/O ports with interrupt capability
– Up to 157 fast I/Os up to 90 MHz
– Up to 159 5 V-tolerant I/Os
• Up to 21 communication interfaces
– Up to 3 × I2C interfaces (SMBus/PMBus)
– Up to 4 USARTs and 4 UARTs (11.25 Mbit/s,
ISO7816 interface, LIN, IrDA, modem control)
–
Udupptloex6I2SSPIfsor(4a5udMiobictsla/ss)s,
2 with muxed full-
accuracy via internal
audio PLL or external clock
– 1 x SAI (serial audio interface)
– 2 × CAN (2.0B Active) and SDIO interface
• Advanced connectivity
– USB 2.0 full-speed device/host/OTG controller
with on-chip PHY
– USB 2.0 high-speed/full-speed device/host/OTG
controller with dedicated DMA, on-chip full-
speed PHY and ULPI
– Dedicated USB power rail enabling on-chip
PHYs operation throughout the entire MCU
power supply range
– 10/100 Ethernet MAC with dedicated DMA:
supports IEEE 1588v2 hardware, MII/RMII
• 8- to 14-bit parallel camera interface up to
54 Mbytes/s
• Cryptographic accelerator
– Hardware accelerator for AES 128, 192 256,
Triple DES, HASH (MD5, SHA-1, SHA-2) and
HMAC
• True random number generator
• CRC calculation unit
• RTC: subsecond accuracy, hardware calendar
• 96-bit unique ID
Table 1. Device summary
Reference
Part number
STM32F479AI, STM32F479II, STM32F479BI,
STM32F479xx STM32F479NI, STM32F479AG, STM32F479IG,
STM32F479BG, STM32F479NG
March 2015
DocID026428 Rev 2
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
For further information contact your local STMicroelectronics sales office.
1/96
www.st.com
List of figures
List of figures
STM32F479xx
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Incompatible board design for LQFP176 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Incompatible board design for LQFP208 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
STM32F479xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
STM32F479xx Multi-AHB matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 21
PDR_ON control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Startup in regulator OFF: slow VDD slope
- power-down reset risen after VCAP_1 , VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . 25
Startup in regulator OFF mode: fast VDD slope
- power-down reset risen before VCAP_1 , VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 25
STM32F47x WLCSP168 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
STM32F47x UFBGA169 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
STM32F47x LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
STM32F47x LQFP208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
STM32F47x TFBGA216 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
WLCSP168 - 168-pin, 4.891 x 5.692 mm, 0.4 mm pitch wafer level chip
scale package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
UFBGA169 - 169-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid
array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
UFBGA169 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 82
LQFP176 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
LQFP176 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 86
LQFP208 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
LQFP208 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
TFBGA216 - thin fine pitch ball grid array 13 × 13 × 0.8mm,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
TFBGA216 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6/96 DocID026428 Rev 2
6 Page Description
STM32F479xx
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1. The timers connected to APB2 are clocked from TIMxCLK up to 180 MHz, while the timers connected to
APB1 are clocked from TIMxCLK either up to 90 MHz or 180 MHz depending on TIMPRE bit configuration
in the RCC_DCKCFGR register.
12/96
DocID026428 Rev 2
12 Page | ||
Seiten | Gesamt 30 Seiten | |
PDF Download | [ STM32F479IG Schematic.PDF ] |
Teilenummer | Beschreibung | Hersteller |
STM32F479IG | ARM 32-bit Cortex-M4 CPU + FPU | STMicroelectronics |
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