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Teilenummer | R4S2426 |
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Beschreibung | 16-Bit Single-Chip Microcomputer | |
Hersteller | Renesas | |
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Gesamt 30 Seiten The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
16
H8S/2426, H8S/2426R, H8S/2424 Group
User’s Manual: Hardware
Renesas 16-Bit Single-Chip Microcomputer
H8S Family / H8S/2400 Series
H8S/2426
H8S/2426R
H8S/2424
R4F2426
R4S2426
R4F2426R
R4S2426R
R4F2424
R4S2424
All information contained in these materials, including products and product
specifications, represents information on the product at the time of publication and is
subject to change by Renesas Electronics Corp. without notice. Please review the
latest information published by Renesas Electronics Corp. through various means,
including the Renesas Electronics Corp. website (http://www.renesas.com).
www.renesas.com
Rev.4.00 Sep 2011
2. Description of Numbers and Symbols
Aspects of the notations for register names, bit names, numbers, and symbolic names in this
manual are explained below.
(1) Overall notation
In descriptions involving the names of bits and bit fields within this manual, the modules and
registers to which the bits belong may be clarified by giving the names in the forms
"module name"."register name"."bit name" or "register name"."bit name".
(2) Register notation
The style "register name"_"instance number" is used in cases where there is more than one
instance of the same function or similar functions.
[Example] CMCSR_0: Indicates the CMCSR register for the compare-match timer of channel 0.
(3) Number notation
Binary numbers are given as B'nnnn (B' may be omitted if the number is obviously binary),
hexadecimal numbers are given as H'nnnn or 0xnnnn, and decimal numbers are given as nnnn.
[Examples] Binary:
B'11 or 11
Hexadecimal: H'EFA0 or 0xEFA0
Decimal:
1234
(4) Notation for active-low
An overbar on the name indicates that a signal or pin is active-low.
[Example] WDTOVF
(4) (2)
14.2.2 Compare Match Control/Status Register_0, _1 (CMCSR_0, CMCSR_1)
CMCSR indicates compare match generation, enables or disables interrupts, and selects the counter
input clock. Generation of a WDTOVF signal or interrupt initializes the TCNT value to 0.
14.3 Operation
14.3.1 Interval Count Operation
When an internal clock is selected with the CKS1 and CKS0 bits in CMCSR and the STR bit in
CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in
CMCNT and the compare match constant register (CMCOR) match, CMCNT is cleared to H'0000
and the CMF flag in CMCSR is set to 1. When the CKS1 and CKS0 bits are set to B'01 at this time,
a f/4 clock is selected.
Rev. 0.50, 10/04, page 416 of 914
(3)
Note: The bit names and sentences in the above figure are examples and have nothing to do
with the contents of this manual.
Page vi of xxx
6 Page 6.3.6 Area 0 Burst ROM Interface Control Register (BROMCRH)
Area 1 Burst ROM Interface Control Register (BROMCRL) .............................. 167
6.3.7 Bus Control Register (BCR) ................................................................................. 168
6.3.8 Address/Data Multiplexed I/O Control Register (MPXCR) ................................. 170
6.3.9 DRAM Control Register (DRAMCR) .................................................................. 171
6.3.10 DRAM Access Control Register (DRACCR)....................................................... 179
6.3.11 Refresh Control Register (REFCR) ...................................................................... 182
6.3.12 Refresh Timer Counter (RTCNT)......................................................................... 185
6.3.13 Refresh Time Constant Register (RTCOR) .......................................................... 185
6.4 Bus Control........................................................................................................................ 186
6.4.1 Area Division........................................................................................................ 186
6.4.2 Bus Specifications ................................................................................................ 187
6.4.3 Memory Interfaces................................................................................................ 189
6.4.4 Chip Select Signals ............................................................................................... 191
6.5 Basic Bus Interface ............................................................................................................ 193
6.5.1 Data Size and Data Alignment.............................................................................. 193
6.5.2 Valid Strobes ........................................................................................................ 195
6.5.3 Basic Timing......................................................................................................... 196
6.5.4 Wait Control ......................................................................................................... 204
6.5.5 Read Strobe (RD) Timing..................................................................................... 205
6.5.6 Extension of Chip Select (CS) Assertion Period................................................... 207
6.6 Address/Data Multiplexed I/O Interface............................................................................ 208
6.6.1 Setting Address/Data Multiplexed I/O Space ....................................................... 208
6.6.2 Address/Data Multiplexing................................................................................... 208
6.6.3 Data Bus ............................................................................................................... 209
6.6.4 Address Hold Signal ............................................................................................. 209
6.6.5 Basic Timing......................................................................................................... 209
6.6.6 Wait Control ......................................................................................................... 218
6.6.7 Read Strobe (RD) Timing..................................................................................... 219
6.6.8 Extension of Chip Select (CS) Assertion Period in Data Cycle............................ 220
6.7 DRAM Interface ................................................................................................................ 222
6.7.1 Setting DRAM Space............................................................................................ 222
6.7.2 Address Multiplexing ........................................................................................... 222
6.7.3 Data Bus ............................................................................................................... 223
6.7.4 Pins Used for DRAM Interface............................................................................. 224
6.7.5 Basic Timing......................................................................................................... 225
6.7.6 Column Address Output Cycle Control ................................................................ 227
6.7.7 Row Address Output State Control....................................................................... 228
6.7.8 Precharge State Control ........................................................................................ 230
6.7.9 Wait Control ......................................................................................................... 231
Page xii of xxx
12 Page | ||
Seiten | Gesamt 30 Seiten | |
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