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APDS-9300 Schematic ( PDF Datasheet ) - AVAGO

Teilenummer APDS-9300
Beschreibung Miniature Ambient Light Photo Sensor
Hersteller AVAGO
Logo AVAGO Logo 




Gesamt 21 Seiten
APDS-9300 Datasheet, Funktion
APDS-9300
Miniature Ambient Light Photo Sensor
with Digital (I2C) Output
Data Sheet
Description
The APDS-9300 is a low-voltage Digital Ambient Light
Photo Sensor that converts light intensity to digital signal
output capable of direct I2C interface. Each device consists
of one broadband photodiode (visible plus infrared) and
one infrared photodiode. Two integrating ADCs convert
the photodiode currents to a digital output that represents
the irradiance measured on each channel. This digital out-
put can be input to a microprocessor where illuminance
(ambient light level) in lux is derived using an empirical
formula to approximate the human-eye response.
Application Support Information
The Application Engineering Group is available to assist
you with the application design associated with APDS-
9300 ambient light photo sensor module. You can contact
them through your local sales representatives for addi-
tional details.
Features
Approximate the human-eye response
Precise Illuminance measurement under diverse
lighting conditions
Programmable Interrupt Function with User-Defined
Upper and Lower Threshold Settings
16-Bit Digital Output with I2C Fast-Mode at 400 kHz
Programmable Analog Gain and Integration Time
Miniature ChipLED Package
Height - 0.55mm
Length - 2.60mm
Width - 2.20mm
50/60-Hz Lighting Ripple Rejection
Low 2.5-V Input Voltage and 1.8-V Digital Output
Low Active Power (0.6 mW Typical) with Power Down
Mode
RoHS Compliant
Applications
Detection of ambient light to control display
backlighting
o Mobile devices – Cell phones, PDAs, PMP
o Computing devices – Notebooks, Tablet PC, Key
board
o Consumer devices – LCD Monitor, Flat-panel TVs,
Video Cameras, Digital Still Camera
Automatic Residential and Commercial Lighting
Management
Automotive instrumentation clusters.
Electronic Signs and Signals






APDS-9300 Datasheet, Funktion
Parameter Measurement Information
t(LOW)
t(R)
t(F)
SCL
t(BUF)
SDA
V IH
V IL
t(HDSTA)
V IH
V IL
t(HDDAT)
t(HIGH)
t(SUDAT)
t(SUSTA)
P
Stop
Condition
S
Start
Condition
Start
t(LOWMEXT)
t(LOWSEXT)
SCL ACK t(LOWMEXT)
SCLACK
S
Stop
t(LOWMEXT)
SCL
Figure 1. Timing Diagrams
SDA
1
SCL
91
t(SUSTO)
P
9
SDA
Start by
Master
A 6 A5 A4 A3 A2 A1 A0 R/W
D7 D6 D5 D4 D3 D2 D1 D0
Frame 1 I2C Slave Address Byte
ACK by
APDS-9300
Frame 2 Command Byte
ACK by
APDS-9300
Figure 2. Example Timing Diagram for I2C Send Byte Format
Stop by
Master
1
SCL
91
9
SDA
A6 A5 A4 A3 A2 A1 A0 R/W
D7 D6 D5 D4 D3 D2 D1 D 0
Start by
Master
Frame 1 I2C Slave Address Byte
ACK by
APDS-9300
NACK by
Master
Frame 2 Data Byte From APDS-9300
Figure 3. Example Timing Diagram for I2C Receive Byte Format
Stop by
Master


6 Page









APDS-9300 pdf, datenblatt
Interrupt Threshold Register (2h - 5h)
The interrupt threshold registers store the values to be used as the high and low trigger points for the comparison func-
tion for interrupt generation. If the value generated by channel 0 crosses below or is equal to the low threshold specified,
an interrupt is asserted on the interrupt pin. If the value generated by channel 0 crosses above the high threshold speci-
fied, an interrupt is asserted on the interrupt pin. Registers THRESHLOWLOW and THRESHLOWHIGH provide the low byte
and high byte, respectively, of the lower interrupt threshold. Registers THRESHHIGHLOW and THRESHHIGHHIGH provide
the low and high bytes, respectively, of the upper interrupt threshold. The high and low bytes from each set of registers
are combined to form a 16–bit threshold value. The interrupt threshold registers default to 00h on power up.
Table 7. Interrupt Threshold Register
Register
Address
THRESHLOWLOW
THRESHLOWHIGH
2h
3h
THRESHHIGHLOW
THRESHHIGHHIGH
4h
5h
Bits
7:0
7:0
7:0
7:0
Description
ADC channel 0 lower byte of the low threshold
ADC channel 0 upper byte of the low threshold
ADC channel 0 lower byte of the high threshold
ADC channel 0 upper byte of the high threshold
NOTE: Since two 8–bit values are combined for a single 16–bit value for each of the high and low interrupt thresholds, the Send Byte protocol
should not be used to write to these registers. Any values transferred by the Send Byte protocol with the MSB set would be interpreted as the
COMMAND field and stored as an address for subsequent read/write operations and not as the interrupt threshold information as desired. The Write
Word protocol should be used to write byte–paired registers. For example, the THRESHLOWLOW and THRESHLOWHIGH registers (as well as the
THRESHHIGHLOW and THRESHHIGHHIGH registers) can be written together to set the 16–bit ADC value in a single transaction.
Interrupt Control Register (6h)
The INTERRUPT register controls the extensive interrupt capabilities of the APDS-9300. The APDS-9300 permits tradi-
tional level–style interrupts. The interrupt persist bit field (PERSIST) provides control over when interrupts occur. A value
of 0 causes an interrupt to occur after every integration cycle regardless of the threshold settings. A value of 1 results
in an interrupt after one integration time period outside the threshold window. A value of N (where N is 2 through15)
results in an interrupt only if the value remains outside the threshold window for N consecutive integration cycles. For
example, if N is equal to 10 and the integration time is 402 ms, then the total time is approximately 4 seconds.
When a level Interrupt is selected, an interrupt is generated whenever the last conversion results in a value outside of
the programmed threshold window. The interrupt is active–low and remains asserted until cleared by writing the COM-
MAND register with the CLEAR bit set.
NOTE: Interrupts are based on the value of Channel 0 only.
Table 8. Interrupt Control Register
7
65
4
6h Resv Resv
INTR
3
21
PERSIST
0
INTERRUPT
Reset Value:
0
00 0 0
00
0
Field
Resv
INTR
PERSIST
Bits
7:6
5:4
3:0
Description
Reserved. Write as 0.
INTR Control Select. This field determines mode of interrupt logic according to Table 9,
below.
Interrupt persistence. Controls rate of interrupts to the host processor as shown in Table 10,
below.
12

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