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APDS-9303 Schematic ( PDF Datasheet ) - AVAGO

Teilenummer APDS-9303
Beschreibung Miniature Ambient Light Photo Sensor
Hersteller AVAGO
Logo AVAGO Logo 




Gesamt 21 Seiten
APDS-9303 Datasheet, Funktion
APDS-9303
Miniature Ambient Light Photo Sensor
with Digital (SMBus) Output
Data Sheet
Description
The APDS-9303 is a low-voltage Digital Ambient Light
Photo Sensor that converts light intensity to digital signal
output capable of direct SMBus interface. Each device
consists of one broadband photodiode (visible plus
infrared) and one infrared photodiode. Two integrating
ADCs convert the photodiode currents to a digital output
that represents the irradiance measured on each channel.
This digital output can be input to a microprocessor where
illuminance (ambient light level) in lux is derived using
an empirical formula to approximate the human-eye
response.
Application Support Information
The Application Engineering Group is available to
assist you with the application design associated with
APDS-9303 ambient light photo sensor module. You can
contact them through your local sales representatives for
additional details.
Features
Approximate the human-eye response
Precise Illuminance measurement under diverse light-
ing conditions
Programmable Interrupt Function with User-Defined
Upper and Lower Threshold Settings
16-Bit Digital Output with SMBus at 100 kHz
Programmable Analog Gain and Integration Time
Miniature ChipLED Package
– Height – 0.55mm
– Length – 2.60mm
– Width – 2.20mm
50/60-Hz Lighting Ripple Rejection
Low Active Power (0.6 mW Typical) with Power Down
Mode
RoHS Compliant
Applications
Detection of ambient light to control display
backlighting
– Mobile devices – Cell phones, PDAs, PMP
– Computing devices – Notebooks, Tablet PC, Key
board
– Consumer devices – LCD Monitor, Flat-panel TVs,
Video Cameras, Digital Still Camera
Automatic Residential and Commercial Lighting
Management
Automotive instrumentation clusters.
Electronic Signs and Signals
Ordering Information
Part Number
APDS-9303-020
Packaging Type
Tape and Reel
Package
6-pins Chipled package
Quantity
2500






APDS-9303 Datasheet, Funktion
Typical Characteristics
1 Spectral Responsivity
Channel 0
0.8 Photodiode
0.6
0.4
Channel 1
0.2 Photodiode
0300 400 500 600 700 800 900 1000 1100
- Wavelength - nm
Figure 4
1.0
0.8
0.6
0.4
0.2
0
-90
Figure 5
Normalized Responsivity Vs.
Angular Displacement * Cl Package
-60 -30
0
30
60
- Angular Displacement - 470 pF
90
PRINCIPLES OF OPERATION
Analog–to–Digital Converter
The APDS-9303 contains two integrating analog-to-digital
converters (ADC) that integrate the currents from the
channel 0 and channel 1 photodiodes. Integration of both
channels occurs simultaneously, and upon completion of
the conversion cycle the conversion result is transferred to
the channel 0 and channel 1 data registers, respectively.
The transfers are double buffered to ensure that invalid
data is not read during the transfer. After the transfer, the
device automatically begins the next integration cycle.
Digital Interface
Interface and control of the APDS-9303 is accomplished
through a two–wire serial interface to a set of registers
that provide access to device control functions and
output data. The serial interface is compatible to SMBUS
bus version 1.1 and 2.0. The APDS-9303 offers three slave
addresses that are selectable via an external pin (ADDR
SEL). The slave address options are shown in Table 1.
Table 1. Slave Address Selection
ADDR SEL
TERMINAL LEVEL
SLAVE
ADDRESS
SMB ALERT
ADDRESS
GND
0101001
0001100
Float
0111001
0001100
VDD
1001001
0001100
NOTE: The Slave Addresses and SMB Alert Address are 7 bits. Please note
the SMBus protocol on the following contents. A read/write bit should
be appended to the slave address by the master device to properly
communicate with the APDS-9303 device.
SMBUS Protocol
Each Send and Write protocol is, essentially, a series of
bytes. A byte sent to the APDS-9303 with the most sig-
nificant bit (MSB) equal to 1 will be interpreted as a
COMMAND byte. The lower four bits of the COMMAND
byte form the register select address (see Table 2), which is
used to select the destination for the subsequent byte(s)
received. The APDS-9303 responds to any Receive Byte
requests with the contents of the register specified by the
stored register select address.
The APDS-9303 implements the following protocols of
the SMBUS 2.0 specification:
Send Byte protocol
Receive Byte protocol
Write Byte protocol
Write Word protocol
Read Word protocol
Block Write protocol
Block Read protocol
When an SMBus Block Write or Block Read is initiated (see
description of COMMAND Register), the byte following
the COMMAND byte is ignored but is a requirement of the
SMBus specification. This field contains the byte count (i.e.
the number of bytes to be transferred). The APDS-9303
device ignores this field and extracts this information by
counting the actual number of bytes transferred before
the Stop condition is detected.
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APDS-9303 pdf, datenblatt
Interrupt Control Register (6h)
The INTERRUPT register controls the extensive interrupt capabilities of the APDS-9303. The APDS-9303 permits both
SMB–Alert style interrupts as well as traditional level–style interrupts. The interrupt persist bit field (PERSIST) provides
control over when interrupts occur. A value of 0 causes an interrupt to occur after every integration cycle regardless
of the threshold settings. A value of 1 results in an interrupt after one integration time period outside the threshold
window. A value of N (where N is 2 through15) results in an interrupt only if the value remains outside the threshold
window for N consecutive integration cycles. For example, if N is equal to 10 and the integration time is 402 ms, then the
total time is approximately 4 seconds.
When a level Interrupt is selected, an interrupt is generated whenever the last conversion results in a value outside
of the programmed threshold window. The interrupt is active–low and remains asserted until cleared by writing the
COMMAND register with the CLEAR bit set.
In SMBAlert mode, the interrupt is similar to the traditional level style and the interrupt line is asserted low. To clear
the interrupt, the host responds to the SMBAlert by performing a modified Receive Byte operation, in which the Alert
Response Address (ARA) is placed in the slave address field, and the APDS-9303 that generated the interrupt responds by
returning its own address in the seven most significant bits of the receive data byte. If more than one device connected
on the bus has pulled the SMBAlert line low, the highest priority (lowest address) device will win communication rights
via standard arbitration during the slave address transfer. If the device loses this arbitration, the interrupt will not be
cleared. The Alert Response Address is 0Ch.
When INTR = 11, the interrupt is generated immediately following the SMBus write operation. Operation then behaves
in an SMBAlert mode, and the software set interrupt may be cleared by an SMBAlert cycle.
NOTE: Interrupts are based on the value of Channel 0 only.
Table 8. Interrupt Control Register
76543210
6h Resv Resv
INTR
PERSIST
INTERRUPT
Reset Value:
0
0
0
0
0
0
0
0
FIELD
Resv
INTR
PERSIST
BITS DESCRIPTION
7:6 Reserved. Write as 0.
5:4 INTR Control Select. This field determines mode of interrupt logic according to Table 9, below.
3:0 Interrupt persistence. Controls rate of interrupts to the host processor as shown in Table 10, below.
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