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GAL20RA10 Schematic ( PDF Datasheet ) - Lattice Semiconductor

Teilenummer GAL20RA10
Beschreibung High-Speed Asynchronous E2CMOS PLD Generic Array Logic
Hersteller Lattice Semiconductor
Logo Lattice Semiconductor Logo 




Gesamt 15 Seiten
GAL20RA10 Datasheet, Funktion
GAL20RA10
High-Speed Asynchronous E2CMOS PLD
Generic Array Logic™
Features
Functional Block Diagram
HIGH PERFORMANCE E2CMOS ® TECHNOLOGY
7.5 ns Maximum Propagation Delay
Fmax = 83.3 MHz
9 ns Maximum from Clock Input to Data Output
TTL Compatible 8 mA Outputs
UltraMOS® Advanced CMOS Technology
50% to 75% REDUCTION IN POWER FROM BIPOLAR
75mA Typical Icc
ACTIVE PULL-UPS ON ALL PINS
E2 CELL TECHNOLOGY
Reconfigurable Logic
Reprogrammable Cells
100% Tested/100% Yields
High Speed Electrical Erasure (<100 ms)
20 Year Data Retention
TEN OUTPUT LOGIC MACROCELLS
Independent Programmable Clocks
Independent Asynchronous Reset and Preset
Registered or Combinatorial with Polarity
Full Function and Parametric Compatibility with
PAL20RA10
PRELOAD AND POWER-ON RESET OF ALL REGISTERS
100% Functional Testability
APPLICATIONS INCLUDE:
State Machine Control
Standard Logic Consolidation
Multiple Clock Logic Designs
ELECTRONIC SIGNATURE FOR IDENTIFICATION
PL
I
I
I
I
I
I
I
I
I
I
8
OLMC
8
OLMC
8
OLMC
8
OLMC
8
OLMC
8
OLMC
8
OLMC
8
OLMC
8
OLMC
8
OLMC
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
Description
OE
The GAL20RA10 combines a high performance CMOS process
with electrically erasable (E2) floating gate technology to provide
the highest speed performance available in the PLD market. Lattice
Semiconductor’s E2CMOS circuitry achieves power levels as low
as 75mA typical I which represents a substantial savings in power
CC
when compared to bipolar counterparts. E2 technology offers high
speed (<100ms) erase times providing the ability to reprogram,
reconfigure or test the devices quickly and efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. The GAL20RA10 is a direct parametric compatible CMOS
replacement for the PAL20RA10 device.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacturing. Therefore, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Pin Configuration
PLCC
4
I5
2 28 26
25
I
I7
23
NC GAL20RA10
I 9 Top View 21
I
I 11
19
12 14 16 18
I/O/Q
I/O/Q
I/O/Q
NC
I/O/Q
I/O/Q
I/O/Q
DIP
PL 1
I
24 Vcc
I/O/Q
I
I GAL
I 20RA10
I6
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I 18 I/O/Q
I I/O/Q
I I/O/Q
I I/O/Q
I I/O/Q
GND 12
13 OE
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com
July 1997
20ra10_02
1






GAL20RA10 Datasheet, Funktion
Specifications GAL20RA10B
Absolute Maximum Ratings(1)
Recommended Operating Conditions
Supply voltage V ....................................... -0.5 to +7V
CC
Input voltage applied ........................... -2.5 to VCC +1.0V
Off-state output voltage applied .......... -2.5 to VCC +1.0V
Storage Temperature ................................. -65 to 150°C
Ambient Temperature with
Power Applied ......................................... -55 to 125°C
1.Stresses above those listed under the Absolute Maximum
Ratingsmay cause permanent damage to the device. These
are stress only ratings and functional operation of the device at
these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).
Commercial Devices:
Ambient Temperature (TA) ............................. 0 to +75°C
Supply voltage (VCC)
with Respect to Ground ..................... +4.75 to +5.25V
Industrial Devices:
Ambient
Temperature
(T )
A
.......................... -40
to
+85°C
Supply voltage (VCC)
with Respect to Ground ..................... +4.50 to +5.50V
DC Electrical Characteristics
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL PARAMETER
CONDITION
MIN. TYP.3 MAX. UNITS
VIL Input Low Voltage
Vss 0.5
VIH Input High Voltage
2.0
IIL1 Input or I/O Low Leakage Current 0V VIN VIL (MAX.)
IIH
Input or I/O High Leakage Current
3.5V VIN VCC
VOL
Output Low Voltage
IOL = MAX. Vin = VIL or VIH
VOH
Output High Voltage
IOH = MAX. Vin = VIL or VIH
2.4
IOL Low Level Output Current
IOH High Level Output Current
IOS2
Output Short Circuit Current
VCC = 5V VOUT = 0.5V TA = 25°C
-50
COMMERCIAL
ICC Operating Power VIL = 0.5V VIH = 3.0V
L -7/-10/-15/-20/-30
Supply Current
ftoggle = 15MHz Outputs Open
75
0.8
Vcc+1
-100
10
0.5
8
-3.2
-135
V
V
µA
µA
V
V
mA
mA
mA
100 mA
INDUSTRIAL
ICC Operating Power
Supply Current
VIL = 0.5V VIH = 3.0V
ftoggle = 15MHz Outputs Open
L -20
75 120 mA
1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Characterized but not 100% tested.
3) Typical values are at Vcc = 5V and TA = 25 °C
6

6 Page









GAL20RA10 pdf, datenblatt
Specifications GAL20RA10
GAL10RA10B-7/-10: Typical AC and DC Characteristic Diagrams
Normalized Tpd vs Vcc
1.2
1.1
1
0.9
0.8
4.50
4.75
5.00
5.25
Supply Voltage (V)
5.50
Normalized Tco vs Vcc
1.2
1.1
1
0.9
0.8
4.50
4.75
5.00
5.25
Supply Voltage (V)
5.50
Normalized Tsu vs Vcc
1.4
1.2
1
0.8
0.6
4.50
4.75
5.00
5.25
Supply Voltage (V)
5.50
Normalized Tpd vs Temp
1.3
1.2
1.1
1
0.9
0.8
0.7
Temperature (deg. C)
Normalized Tco vs Temp
1.3
1.2
1.1
1
0.9
0.8
0.7
Temperature (deg. C)
Normalized Tsu vs Temp
1.6
1.4
1.2
1
0.8
0.6
Temperature (deg. C)
Delta Tpd vs # of Outputs
Switching
0
-0.5
-1
-1.5
1 2 3 4 5 6 7 8 9 10
Number of Outputs Switching
Delta Tco vs # of Outputs
Switching
0
-0.5
-1
-1.5
-2
1 2 3 4 5 6 7 8 9 10
Number of Outputs Switching
Delta Tpd vs Output
Loading
8
6 RISE
4 FALL
2
0
-2
-4
0 50 100
Output Loading (pF)
150
Delta Tco vs Output
Loading
8
6 RISE
4 FALL
2
0
-2
-4
0 50 100
Output Loading (pF)
150
12

12 Page





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