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GAL20LV8D-7LJ Schematic ( PDF Datasheet ) - Lattice Semiconductor

Teilenummer GAL20LV8D-7LJ
Beschreibung Low Voltage E2CMOS PLD Generic Array Logic
Hersteller Lattice Semiconductor
Logo Lattice Semiconductor Logo 




Gesamt 17 Seiten
GAL20LV8D-7LJ Datasheet, Funktion
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GAL20LV8
Low Voltage E2CMOS PLD
Generic Array Logic™
Features
Functional Block Diagram
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— 3.5 ns Maximum Propagation Delay
— Fmax = 250 MHz
— 2.5 ns Maximum from Clock Input to Data Output
— UltraMOS® Advanced CMOS Technology
— TTL-Compatible Balanced 8mA Output Drive
• 3.3V LOW VOLTAGE 20V8 ARCHITECTURE
— JEDEC-Compatible 3.3V Interface Standard
— 5V Compatible Inputs
• ACTIVE PULL-UPS ON ALL PINS
• E2 CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• EIGHT OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— Glue Logic for 3.3V Systems
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
Description
The GAL20LV8D, at 3.5 ns maximum propagation delay time,
provides the highest speed performance available in the PLD
market. The GAL20LV8D is manufactured using Lattice
Semiconductor's advanced 3.3V E2CMOS process, which com-
bines CMOS with Electrically Erasable (E2) floating gate technology.
High speed erase times (<100ms) allow the devices to be repro-
grammed quickly and efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. An important subset of the many architecture configura-
tions possible with the GAL20LV8D are the PAL architectures listed
in the table of the macrocell description section. GAL20LV8D
devices are capable of emulating any of these PAL architectures
with full function/fuse map compatibility.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
I/CLK
I
I
I
I
I
I
I
I
I
I
IMUX
CLK
8 OLMC
8 OLMC
8 OLMC
8 OLMC
8 OLMC
8 OLMC
8 OLMC
8 OLMC
OE
IMUX
Pin Configuration
PLCC
4
I5
I
I7
NC
I9
I
I 11
12
2 28
GAL20LV8D
Top View
14 16
26
25 I/O/Q
I/O/Q
23 I/O/Q
NC
21 I/O/Q
I/O/Q
19 I/O/Q
18
I
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
I/OE
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
March 2000
20lv8_05
1






GAL20LV8D-7LJ Datasheet, Funktion
Specifications GAL20LV8
Complex Mode
In the Complex mode, macrocells are configured as output only or signs requiring eight I/Os can be implemented in the Registered
I/O functions.
mode.
Architecture configurations available in this mode are similar to the
common 20L8 and 20P8 devices with programmable polarity in
each macrocell.
All macrocells have seven product terms per output. One product
term is used for programmable output enable control. Pins 2 and
16 are always available as data inputs into the AND array.
Up to six I/Os are possible in this mode. Dedicated inputs or outputs
can be implemented as subsets of the I/O function. The two outer
most macrocells (pins 18 & 26) do not have input capability. De-
The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram on the following page.
XOR
Combinatorial I/O Configuration for Complex Mode
- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1.
- Pin 19 through Pin 25 are configured to this function.
XOR
Combinatorial Output Configuration for Complex Mode
- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1.
- Pin 18 and Pin 26 are configured to this function.
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
6

6 Page









GAL20LV8D-7LJ pdf, datenblatt
Switching Waveforms
INPUT or
I/O FEEDBACK
COMBINATIONAL
OUTPUT
VALID INPUT
tpd
Combinatorial Output
INPUT or
I/O FEEDBACK
COMBINATIONAL
OUTPUT
tdis ten
Input or I/O to Output Enable/Disable
Specifications GAL20LV8
INPUT or
I/O FEEDBACK
CLK
REGISTERED
OUTPUT
VALID INPUT
tsu th
tco
1/fmax
(external fdbk)
Registered Output
OE
REGISTERED
OUTPUT
tdis ten
OE to Output Enable/Disable
twh twl
CLK
1/fmax
(w/o fb)
Clock Width
CLK
REGISTERED
FEEDBACK
1/fmax (internal fdbk)
tcf tsu
fmax with Feedback
12

12 Page





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