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GAL18V10B-20LJ Schematic ( PDF Datasheet ) - Lattice Semiconductor

Teilenummer GAL18V10B-20LJ
Beschreibung High Performance E2CMOS PLD Generic Array Logic
Hersteller Lattice Semiconductor
Logo Lattice Semiconductor Logo 




Gesamt 16 Seiten
GAL18V10B-20LJ Datasheet, Funktion
GAL18V10
High Performance E2CMOS PLD
Generic Array Logic™
Features
HIGH PERFORMANCE E2CMOS® TECHNOLOGY
7.5 ns Maximum Propagation Delay
Fmax = 111 MHz
5.5 ns Maximum from Clock Input to Data Output
TTL Compatible 16 mA Outputs
UltraMOS® Advanced CMOS Technology
LOW POWER CMOS
75 mA Typical Icc
ACTIVE PULL-UPS ON ALL PINS
E2 CELL TECHNOLOGY
Reconfigurable Logic
Reprogrammable Cells
100% Tested/100% Yields
High Speed Electrical Erasure (<100ms)
20 Year Data Retention
TEN OUTPUT LOGIC MACROCELLS
Uses Standard 22V10 Macrocell Architecture
Maximum Flexibility for Complex Logic Designs
PRELOAD AND POWER-ON RESET OF REGISTERS
100% Functional Testability
APPLICATIONS INCLUDE:
DMA Control
State Machine Control
High Speed Graphics Processing
Standard Logic Speed Upgrade
ELECTRONIC SIGNATURE FOR IDENTIFICATION
Description
The GAL18V10, at 7.5 ns maximum propagation delay time, com-
bines a high performance CMOS process with Electrically Eras-
able (E2) floating gate technology to provide a very flexible 20-pin
PLD. CMOS circuitry allows the GAL18V10 to consume much less
power when compared to its bipolar counterparts. The E2 technol-
ogy offers high speed (<100ms) erase times, providing the ability
to reprogram or reconfigure the device quickly and efficiently.
By building on the popular 22V10 architecture, the GAL18V10
eliminates the learning curve usually associated with using a new
device architecture. The generic architecture provides maximum
design flexibility by allowing the Output Logic Macrocell (OLMC)
to be configured by the user. The GAL18V10 OLMC is fully com-
patible with the OLMC in standard bipolar and CMOS 22V10 de-
vices.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Functional Block Diagram
I/CLK
I
I
I
I
I
I
I
RESET
8
OLMC
8
OLMC
8
OLMC
8
OLMC
10
OLMC
10
OLMC
8
OLMC
8
OLMC
8
OLMC
8
OLMC
PRESET
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
Pin Configuration
PLCC
I
I4
I I/CLK Vcc I/O/Q
2 20
18 I/O/Q
I I/O/Q
I 6 GAL18V10 16 I/O/Q
I
Top View
I/O/Q
I8
14 I/O/Q
9 11 13
I/O/Q GND I/O/Q I/O/Q I/O/Q
DIP
I/CLK
I
I
I
I
I
I
I
I/O/Q
GND
1 20 Vcc
I/O/Q
GAL
18V10
5
I/O/Q
I/O/Q
I/O/Q
15 I/O/Q
I/O/Q
I/O/Q
I/O/Q
10 11 I/O/Q
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com
July 1997
18v10_03
1






GAL18V10B-20LJ Datasheet, Funktion
Specifications GAL18V10B
Absolute Maximum Ratings(1)
Recommended Operating Conditions
Supply voltage V ....................................... -0.5 to +7V
CC
Input voltage applied ........................... -2.5 to VCC +1.0V
Off-state output voltage applied .......... -2.5 to VCC +1.0V
Storage Temperature ................................. -65 to 150°C
Ambient Temperature with
Power Applied ......................................... -55 to 125°C
1. Stresses above those listed under the Absolute Maximum
Ratingsmay cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).
Commercial Devices:
Ambient Temperature (TA) ............................. 0 to +75°C
Supply voltage (VCC)
with Respect to Ground ..................... +4.75 to +5.25V
DC Electrical Characteristics
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL PARAMETER
CONDITION
MIN. TYP.3 MAX. UNITS
VIL
VIH
IIL1
IIH
VOL
VOH
IOL
IOH
IOS2
Input Low Voltage
Input High Voltage
Input or I/O Low Leakage Current
Input or I/O High Leakage Current
Output Low Voltage
Output High Voltage
Low Level Output Current
High Level Output Current
Output Short Circuit Current
0V VIN VIL (MAX.)
3.5V VIN VCC
IOL = MAX. Vin = VIL or VIH
IOH = MAX. Vin = VIL or VIH
VCC = 5V VOUT = 0.5V TA = 25°C
Vss 0.5
2.0
2.4
30
COMMERCIAL
ICC Operating Power
Supply Current
VIL = 0.5V VIH = 3.0V
ftoggle = 15MHz Outputs Open
L -7/-10/-15/-20
75
0.8
Vcc+1
100
10
0.5
16
3.2
130
V
V
µA
µA
V
V
mA
mA
mA
115 mA
1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Characterized but not 100% tested.
3) Typical values are at Vcc = 5V and TA = 25 °C
6

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GAL18V10B-20LJ pdf, datenblatt
Specifications GAL18V10
Electronic Signature
Output Register Preload
An electronic signature is provided in every GAL18V10 device. It
contains 64 bits of reprogrammable memory that can contain user-
defined data. Some uses include user ID codes, revision numbers,
or inventory control. The signature data is always available to the
user independent of the state of the security cell.
Security Cell
A security cell is provided in every GAL18V10 device to prevent
unauthorized copying of the array patterns. Once programmed,
this cell prevents further read access to the functional bits in the
device. This cell can only be erased by re-programming the de-
vice, so the original configuration can never be examined once this
cell is programmed. The Electronic Signature is always available
to the user, regardless of the state of this control cell.
When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because certain events
may occur during system operation that throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.). To
test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired (i.e.,
illegal) state into the registers. Then the machine can be sequenced
and the outputs tested for correct next state conditions.
The GAL18V10 device includes circuitry that allows each registered
output to be synchronously set either high or low. Thus, any present
state condition can be forced for test sequencing. If necessary,
approved GAL programmers capable of executing test vectors
perform output register preload automatically.
Latch-Up Protection
Input Buffers
GAL18V10 devices are designed with an on-board charge pump
to negatively bias the substrate. The negative bias is of sufficient
magnitude to prevent input undershoots from causing the circuitry
to latch. Additionally, outputs are designed with n-channel pullups
instead of the traditional p-channel pullups to eliminate any pos-
sibility of SCR induced latching.
Device Programming
GAL devices are programmed using a Lattice Semiconductor-
approved Logic Programmer, available from a number of manu-
facturers (see the the GAL Development Tools section). Complete
programming of the device takes only a few seconds. Erasing of
the device is transparent to the user, and is done automatically as
part of the programming cycle.
GAL18V10 devices are designed with TTL level compatible input
buffers. These buffers have a characteristically high impedance,
and present a much lighter load to the driving logic than bipolar TTL
devices.
The input and I/O pins also have built-in active pull-ups. As a result,
floating inputs will float to a TTL high (logic 1). However, Lattice
Semiconductor recommends that all unused inputs and tri-stated
I/O pins be connected to an adjacent active input, Vcc, or ground.
Doing so will tend to improve noise immunity and reduce Icc for the
device.
Typical Input Current
0
-20
-40
-60
0
1.0 2.0 3.0
Input Voltage (Volts)
4.0
5.0
12

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