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RDA5820 Schematic ( PDF Datasheet ) - RDA

Teilenummer RDA5820
Beschreibung SINGLE-CHIP BROADCAST FM TRANSCEIVER
Hersteller RDA
Logo RDA Logo 




Gesamt 28 Seiten
RDA5820 Datasheet, Funktion
RDA5820
SINGLE-CHIP BROADCAST FM TRANSCEIVER Rev.1.3Oct.2008
1 General Description
The RDA5820 is a single-chip broadcast FM
transceiver with fully integrated synthesizer, IF
selectivity and MPX decoder. The chip uses the
CMOS process, support multi-interface and
require the least external component. The
package size is 4X4mm and is completely
adjustment-free. All these make it very suitable for
portable devices.
The RDA5820 has a powerful low-IF digital audio
processor, this make it have optimum sound
quality with varying reception conditions.
The RDA5820 use RDA patented dual
synthesizers, all digital transmit structure, this
make it have perfectly transmition performance
and agility.
Figure 1-1. RDA5820 Top View
The RDA5820 support 65M~115M frequency band receive and transmit, integrate 4K memory, these
make it can be used in simple wireless control appliance such as toy.
1.1 Features
l CMOS single-chip fully-integrated FM transceiver
l Low power consumption
Ø Total current consumption lower than 20mA at
3.0V power supply
l Support worldwide and campus frequency band
Ø 65 -115 MHz
l Digital low-IF tuner
Ø Image-reject down-converter
Ø High performance A/D converter
Ø IF selectivity performed internally
l Fully integrated digital frequency synthesizer
Ø Fully integrated on-chip RF and IF VCO
Ø Fully integrated on-chip loop filter
l All digital transmitter
l Autonomous search tuning
l Support integrated Rx/Tx PCB antenna
l Support SNR FM searching
l Include 4K memory
l Support 32.768KHz crystal oscillator
l Digital auto gain control (AGC)
l Digital adaptive noise cancellation
Ø Mono/stereo switch
Ø Soft mute
Ø High cut
l Programmable de-emphasis (50/75 µs)
l Receive signal strength indicator (RSSI)
l Bass boost
l Volume control
l Support I2S digital transmitter
l Support audio power amplifier ( 32Ω resistance
Copyright © RDA Microelectronics Inc. 2006. All rights are reserved.
The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in
part without prior written permission of RDA.






RDA5820 Datasheet, Funktion
RDA Microelectronics, Inc.
3.8 Synthesizer2
The frequency synthesizer 2 (including
synthesizer2 and VCO2 ) generates clock
signals for ADC under FM RX (receive) mode.
The frequency synthesizer2 is also the FM
transmit core. The digital signals (audio) are
directly added on it.
3.9 Power Supply
RDA5820 FM Transceiver V1.3
The I2C interface is compliant to I2C Bus
Specification 2.1. It includes two pins: SCLK and
SDIO. A I2C interface transfer begins with START
condition, a command byte and data bytes, each
byte has a followed ACK (or NACK) bit, and ends
with STOP condition. The command byte includes
a 7-bit chip address (0010001b) and a R/W bit.
The ACK (or NACK) is always sent out by receiver.
When in write transfer, data bytes is written out
from MCU, and when in read transfer, data bytes
is read out from RDA5820.
Details refer to RDA5820 Programming Guide.
The RDA5820 integrated one LDO which supplies
power to the chip. The external supply voltage
range is 2.7-5.5 V.
3.10 RESET and Control Interface select
The RDA5820 is RESET itself When VIO is Power
up. And also support soft reset by trigger 02H
BIT1 from 0 to 1. The control interface is selected
by MODE Pin. The MODE Pin is low ,I2C
Interface is selected. The MODE Pin is set to VIO,
SPI Interface is selected.
3.11 Control Interface
The RDA5820 supports three-wire and I2C control
interface. User could select either of them to
program the chip.
The three-wire interface is a standard SPI
interface. It includes three pins: SEN, SCLK and
SDIO. Each register write is 25-bit long, including
4-bit high register address, a r/w bit, 4-bit low
register address, and 16-bit data (MSB is the first
bit). RDA5820 samples command byte and data
at posedge of SCLK. Each register read is also
25-bit long, including 4-bit high register address, a
r/w bit, 4-bit low register address, and 16-bit data
(MSB is the first bit) from RDA5820. The turn
around cycle between command byte from MCU
and data from RDA5820 is a half cycle. RDA5820
samples command byte at posedge of SCLK, and
output data also at posedge of SCLK.
SCK
WS
SD
1 SCK
MSB
LEFT CHANNEL
LSB
3.12 I2S Audio Data Interface
The RDA5820 supports I2S (Inter_IC Sound Bus)
audio interface. The interface is fully compliant
with I2S bus specification. When setting I2SEN bit
high, RDA5820 will output SCK, WS, SD signals
from GPIO3, GPIO1, GPIO2 as I2S master and
transmitter, the sample rate is 48Kbps
44.1kbps,32kbps.. RDA5820 also support as
I2S slaver mode and transmitter, the sample rate
is less than 100kbps.
3.13 GPIO Outputs
The RDA5820 has three GPIOs. The function of
GPIOs could programmed with bits GPIO1[1:0],
GPIO2[1:0], GPIO3[1:0] and I2SEN.
If I2SEN is set to low, GPIO pins could be
programmed to output low or high or high-Z, or be
programmed to output interrupt and stereo
indicator with bits GPIO1[1:0], GPIO2[1:0],
GPIO3[1:0]. GPIO2 could be programmed to
output a low interrupt (interrupt will be generated
only with interrupt enable bit STCIEN is set to high)
when seek/tune process completes. GPIO3 could
be programmed to output stereo indicator bit ST.
Constant low, high or high-Z functionality is
available regardless of the state of VA and VD
supplies or the ENABLE bit.
1 SCK
MSB
RIGHT CHANNEL
LSB
Figure 3-2. I2S Digital Audio Format
The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in
part without prior written permission of RDA.
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RDA5820 pdf, datenblatt
RDA Microelectronics, Inc.
RDA5820 FM Transceiver V1.3
7.2 I2C Interface Timing
Table 7-2 I2C Interface Timing Characteristics
(VDD = 2.7 to 5.5 V, TA = -25 to 85 °C, unless otherwise specified)
PARAMETER
SYMBOL TEST CONDITION
MIN
TYP MAX UNIT
SCLK Frequency
SCLK High Time
SCLK Low Time
Setup Time for START Condition
Hold Time for START Condition
Setup Time for STOP Condition
SDIO Input to SCLKSetup
SDIO Input to SCLKHold
STOP to START Time
SDIO Output Fall Time
SDIO Input, SCLK Rise/Fall Time
Input Spike Suppression
SCLK, SDIO Capacitive Loading
Digital Input Pin Capacitance
fscl
thigh
tlow
tsu:sta
thd:sta
tsu:sto
tsu:dat
thd:dat
tbuf
tf:out
tr:in / tf:in
tsp
Cb
0
0.6
1.3
0.6
0.6
0.6
100
0
1.3
20+0.1Cb
20+0.1Cb
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
400 KHz
- µs
- µs
- µs
- µs
- µs
- ns
900 ns
- µs
250 ns
300 ns
50 ns
50 pF
5 pF
Figure 7-3. I2C Interface Write Timing Diagram
Figure 7-4. I2C Interface Read Timing Diagram
The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in
part without prior written permission of RDA.
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