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Teilenummer | GAL16VP8 |
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Beschreibung | High-Speed E2CMOS PLD Generic Array Logic | |
Hersteller | Lattice Semiconductor | |
Logo | ||
Gesamt 17 Seiten GAL16VP8
High-Speed E2CMOS PLD
Generic Array Logic™
Features
• HIGH DRIVE E2CMOS® GAL® DEVICE
— TTL Compatible 64 mA Output Drive
— 15 ns Maximum Propagation Delay
— Fmax = 80 MHz
— 10 ns Maximum from Clock Input to Data Output
— UltraMOS® Advanced CMOS Technology
• ENHANCED INPUT AND OUTPUT FEATURES
— Schmitt Trigger Inputs
— Programmable Open-Drain or Totem-Pole Outputs
— Active Pull-Ups on All Inputs and I/O pins
• E2 CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• EIGHT OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
— Architecturally Compatible with Standard GAL16V8
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— Ideal for Bus Control & Bus Arbitration Logic
— Bus Address Decode Logic
— Memory Address, Data and Control Circuits
— DMA Control
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
Description
The GAL16VP8, with 64 mA drive capability and 15 ns maximum
propagation delay time is ideal for Bus and Memory control appli-
cations. The GAL16VP8 is manufactured using Lattice
Semiconductor's advanced E2CMOS process which combines
CMOS with Electrically Erasable (E2) floating gate technology. High
speed erase times (<100ms) allow the devices to be reprogrammed
quickly and efficiently.
System bus and memory interfaces require control logic before
driving the bus or memory interface signals. The GAL16VP8
combines the familiar GAL16V8 architecture with bus drivers as
its outputs. The generic architecture provides maximum design flex-
ibility by allowing the Output Logic Macrocell (OLMC) to be con-
figured by the user. The 64mA output drive eliminates the need for
additional devices to provide bus driving capability.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Functional Block Diagram
I/CLK
CLK
8 OLMC
I
8 OLMC
I
8 OLMC
I
8 OLMC
I
8 OLMC
I
8 OLMC
I
8 OLMC
I
8 OLMC
I
OE
I
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/OE
Pin Configuration
PLCC
DIP
I/CLK 1
20 I
I
I4
I I/CLK I I/O/Q
2 20
18
I/O/Q
Vcc
I6
I
GAL16VP8
Top View
I/O/Q
16 I/O/Q
GND
I8
9
14 I/O/Q
11 13
I I/OE I/O/Q I/O/Q I/O/Q
I
I GAL
I 16VP8
Vcc 5
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I 15 GND
I I/O/Q
I I/O/Q
I I/O/Q
I/OE 10
11 I/O/Q
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
December 1997
16vp8_03
1
Specifications GAL16VP8
Complex Mode
In the Complex mode, macrocells are configured as output only or
I/O functions.
Up to six I/Os are possible in this mode. Dedicated inputs or outputs
can be implemented as subsets of the I/O function. The two outer
most macrocells (pins 11 & 19) do not have input capability. De-
signs requiring eight I/Os can be implemented in the Registered
mode.
All macrocells have seven product terms per output. One prod-
uct term is used for programmable output enable control. Pins 1
and 10 are always available as data inputs into the AND array.
The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram on the following page.
XOR
Combinatorial I/O Configuration for Complex Mode
- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1 has no effect on this mode.
- AC2=1 defines totem pole output.
- AC2=0 defines open-drain output.
- Pin 12 through Pin 18 are configured to this function.
XOR
Combinatorial Output Configuration for Complex Mode
- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1 has no effect on this mode.
- AC2=1 defines totem pole output.
- AC2=0 defines open-drain output.
- Pin 11 and Pin 19 are configured to this function.
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
6
6 Page Switching Waveforms
INPUT or
I/O FEEDBACK
COMBINATIONAL
OUTPUT
VALID INPUT
tpd
Combinatorial Output
INPUT or
I/O FEEDBACK
COMBINATIONAL
OUTPUT
tdis ten
Input or I/O to Output Enable/Disable
Specifications GAL16VP8
INPUT or
I/O FEEDBACK
CLK
REGISTERED
OUTPUT
VALID INPUT
tsu th
tco
1/fmax
(external fdbk)
Registered Output
OE
REGISTERED
OUTPUT
tdis ten
OE to Output Enable/Disable
twh twl
CLK
1/fmax
(w/o fb)
Clock Width
CLK
REGISTERED
FEEDBACK
1/fmax (internal fdbk)
tcf tsu
fmax with Feedback
12
12 Page | ||
Seiten | Gesamt 17 Seiten | |
PDF Download | [ GAL16VP8 Schematic.PDF ] |
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