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GAL16V8C-7LJI Schematic ( PDF Datasheet ) - Lattice Semiconductor

Teilenummer GAL16V8C-7LJI
Beschreibung High Performance E2CMOS PLD Generic Array Logic
Hersteller Lattice Semiconductor
Logo Lattice Semiconductor Logo 




Gesamt 22 Seiten
GAL16V8C-7LJI Datasheet, Funktion
GAL16V8
High Performance E2CMOS PLD
Generic Array Logic™
Features
HIGH PERFORMANCE E2CMOS® TECHNOLOGY
3.5 ns Maximum Propagation Delay
Fmax = 250 MHz
3.0 ns Maximum from Clock Input to Data Output
UltraMOS® Advanced CMOS Technology
50% to 75% REDUCTION IN POWER FROM BIPOLAR
75mA Typ Icc on Low Power Device
45mA Typ Icc on Quarter Power Device
ACTIVE PULL-UPS ON ALL PINS
E2 CELL TECHNOLOGY
Reconfigurable Logic
Reprogrammable Cells
100% Tested/100% Yields
High Speed Electrical Erasure (<100ms)
20 Year Data Retention
EIGHT OUTPUT LOGIC MACROCELLS
Maximum Flexibility for Complex Logic Designs
Programmable Output Polarity
Also Emulates 20-pin PAL® Devices with Full
Function/Fuse Map/Parametric Compatibility
PRELOAD AND POWER-ON RESET OF ALL REGISTERS
100% Functional Testability
APPLICATIONS INCLUDE:
DMA Control
State Machine Control
High Speed Graphics Processing
Standard Logic Speed Upgrade
ELECTRONIC SIGNATURE FOR IDENTIFICATION
Description
The GAL16V8, at 3.5 ns maximum propagation delay time, com-
bines a high performance CMOS process with Electrically Eras-
able (E2) floating gate technology to provide the highest speed
performance available in the PLD market. High speed erase times
(<100ms) allow the devices to be reprogrammed quickly and ef-
ficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. An important subset of the many architecture configura-
tions possible with the GAL16V8 are the PAL architectures listed
in the table of the macrocell description section. GAL16V8 devices
are capable of emulating any of these PAL architectures with full
function/fuse map/parametric compatibility.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Functional Block Diagram
I/CLK
CLK
I
I
I
I
I
I
I
I
Pin Configuration
I
I4
PLCC
I I/CLK Vcc I/O/Q
2 20
18
I/O/Q
I GAL16V8 I/O/Q
I6
16 I/O/Q
Top View
I I/O/Q
I8
9
14 I/O/Q
11 13
I GND I/OE I/O/Q I/O/Q
I/CLK
I
I
I
I
I
I
I
I
GND
SOIC
1 20
GAL
5 16V8
Top 15
View
10 11
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/OE
8 OLMC
8 OLMC
8 OLMC
8 OLMC
8 OLMC
8 OLMC
8 OLMC
8 OLMC
OE
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/OE
DIP
I/CLK
I
I
I
I
I
I
I
I
GND
1 20 Vcc
I/O/Q
GAL
16V8
5
I/O/Q
I/O/Q
I/O/Q
15 I/O/Q
I/O/Q
I/O/Q
I/O/Q
10 11 I/OE
Copyright © 2001 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
May 2001
16v8_08
1






GAL16V8C-7LJI Datasheet, Funktion
Specifications GAL16V8
Complex Mode
In the Complex mode, macrocells are configured as output only or bility. Designs requiring eight I/O's can be implemented in the
I/O functions.
Registered mode.
Architecture configurations available in this mode are similar to the All macrocells have seven product terms per output. One product
common 16L8 and 16P8 devices with programmable polarity in term is used for programmable output enable control. Pins 1 and
each macrocell.
11 are always available as data inputs into the AND array.
Up to six I/O's are possible in this mode. Dedicated inputs or The JEDEC fuse numbers including the UES fuses and PTD fuses
outputs can be implemented as subsets of the I/O function. The are shown on the logic diagram on the following page.
two outer most macrocells (pins 12 & 19) do not have input capa-
XOR
Combinatorial I/O Configuration for Complex Mode
- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1.
- Pin 13 through Pin 18 are configured to this function.
XOR
Combinatorial Output Configuration for Complex Mode
- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1.
- Pin 12 and Pin 19 are configured to this function.
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
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GAL16V8C-7LJI pdf, datenblatt
SpSepceifcicifaictaiotinosnGs GALA1L61V68VD8
AC Switching Characteristics
Over Recommended Operating Conditions
TEST
PARAM. COND1.
DESCRIPTION
tpd A Input or I/O to Comb. Output
tco A Clock to Output Delay
tcf2 — Clock to Feedback Delay
tsu — Setup Time, Input or Fdbk before Clk
th — Hold Time, Input or Fdbk after Clk
A Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)
COM / IND COM / IND IND COM / IND
-10 -15 -20 -25
UNITS
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
3 10 3 15 3 20 3 25 ns
2 7 2 10 2 11 2 12 ns
— 6 — 8 — 9 — 10 ns
7.5 — 12 — 13 — 15 — ns
0 — 0— 0—
66.7 — 45.5 — 41.6 —
0 — ns
37 — MHz
fmax3 A Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)
71.4 — 50 — 45.4 — 40 — MHz
A Maximum Clock Frequency with
No Feedback
83.3 — 62.5 — 50 — 41.6 — MHz
twh — Clock Pulse Duration, High
twl — Clock Pulse Duration, Low
ten B Input or I/O to Output Enabled
t B OE to Output Enabled
tdis C Input or I/O to Output Disabled
t C OE to Output Disabled
6 — 8 — 10 — 12 — ns
6 — 8 — 10 — 12 — ns
1 10 — 15 — 18 — 20 ns
1 10 — 15 — 18 — 20 ns
1 10 — 15 — 18 — 20 ns
1 10 — 15 — 18 — 20 ns
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.
3) Refer to fmax Descriptions section. Characterized but not 100% tested.
Capacitance (TA = 25°C, f = 1.0 MHz)
SYMBOL
PARAMETER
CI Input Capacitance
C I/O Capacitance
I/O
*Characterized but not 100% tested.
MAXIMUM*
8
8
UNITS
pF
pF
TEST CONDITIONS
VCC = 5.0V, VI = 2.0V
V = 5.0V, V = 2.0V
CC I/O
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