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C8051F301 Schematic ( PDF Datasheet ) - Silicon Laboratories

Teilenummer C8051F301
Beschreibung Mixed Signal ISP Flash MCU Family
Hersteller Silicon Laboratories
Logo Silicon Laboratories Logo 




Gesamt 30 Seiten
C8051F301 Datasheet, Funktion
C8051F300/1/2/3/4/5
Mixed Signal ISP Flash MCU Family
Analog Peripherals
- 8-Bit ADC ('F300/2 only)
Up to 500 ksps
Up to 8 external inputs
Programmable amplifier gains of 4, 2, 1, & 0.5
VREF from external pin or VDD
Built-in temperature sensor
External conversion start input
- Comparator
Programmable hysteresis and response time
Configurable as interrupt or reset source
Low current (<0.5 µA)
On-chip Debug
- On-chip debug circuitry facilitates full speed,
non-intrusive in-system debug (no emulator
required)
- Provides breakpoints, single stepping,
inspect/modify memory and registers
- Superior performance to emulation systems using
ICE-chips, target pods, and sockets
- Complete development kit
Supply Voltage 2.7 to 3.6 V
- Typical operating current: 6.6 mA @ 25 MHz;
14 µA @ 32 kHz
- Typical stop mode current: 0.1 µA
- Temperature range: –40 to +85 °C
High Speed 8051 µc Core
- Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
- Up to 25 MIPS throughput with 25 MHz clock
- Expanded interrupt handler
Memory
- 256 bytes internal data RAM
- Up to 8 kB (‘F300/1/2/3), 4 kB (‘F304), or 2 kB
(‘F305) Flash; 512 bytes are reserved in the 8 kB
devices
Digital Peripherals
- 8 Port I/O; All 5 V tolerant with high sink current
- Hardware enhanced UART and SMBus™ serial
ports
- Three general-purpose 16-bit counter/timers
- 16-bit programmable counter array (PCA) with three
capture/compare modules
- Real time clock mode using PCA or timer and
external clock source
Clock Sources
- Internal oscillator: 24.5 MHz with ±2% accuracy
supports UART operation
- External oscillator: Crystal, RC, C, or clock (1 or 2
pin modes)
- Can switch between clock sources on-the-fly; Useful
in power saving modes
11-Pin QFN or 14-Pin SOIC Package
- QFN Size = 3x3 mm
ANALOG
PERIPHERALS
A 8-bit
M PGA 500 ksps
U
X
ADC
C8051F300/2 only
TEMP
+ SENSOR
- VOLTAGE COMPARATOR
DIGITAL I/O
UART
SMBus
PCA
Timer 0
Timer 1
Timer 2
PROGRAMMABLE PRECISION INTERNAL
OSCILLATOR
HIGH-SPEED CONTROLLER CORE
8/4/2 kBytes
ISP Flash
12
INTERRUPTS
8051 CPU
(25MIPS)
DEBUG
CIRCUITRY
256 B SRAM
POR WDT
Rev. 2.9 7/08
Copyright © 2008 by Silicon Laboratories
C8051F300/1/2/3/4/5






C8051F301 Datasheet, Funktion
C8051F300/1/2/3/4/5
NOTES:
6 Rev. 2.9

6 Page









C8051F301 pdf, datenblatt
C8051F300/1/2/3/4/5
SFR Definition 15.4. TL0: Timer 0 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
SFR Definition 15.5. TL1: Timer 1 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
SFR Definition 15.6. TH0: Timer 0 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
SFR Definition 15.7. TH1: Timer 1 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
SFR Definition 15.8. TMR2CN: Timer 2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
SFR Definition 15.9. TMR2RLL: Timer 2 Reload Register Low Byte . . . . . . . . . . . . . 154
SFR Definition 15.10. TMR2RLH: Timer 2 Reload Register High Byte . . . . . . . . . . . 154
SFR Definition 15.11. TMR2L: Timer 2 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
SFR Definition 15.12. TMR2H Timer 2 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
SFR Definition 16.1. PCA0CN: PCA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
SFR Definition 16.2. PCA0MD: PCA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
SFR Definition 16.3. PCA0CPMn: PCA Capture/Compare Mode . . . . . . . . . . . . . . . 169
SFR Definition 16.4. PCA0L: PCA Counter/Timer Low Byte . . . . . . . . . . . . . . . . . . . 170
SFR Definition 16.5. PCA0H: PCA Counter/Timer High Byte . . . . . . . . . . . . . . . . . . 170
SFR Definition 16.6. PCA0CPLn: PCA Capture Module Low Byte . . . . . . . . . . . . . . . 171
SFR Definition 16.7. PCA0CPHn: PCA Capture Module High Byte . . . . . . . . . . . . . . 171
C2 Register Definition 17.1. C2ADD: C2 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
C2 Register Definition 17.2. DEVICEID: C2 Device ID . . . . . . . . . . . . . . . . . . . . . . . . 173
C2 Register Definition 17.3. REVID: C2 Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . 174
C2 Register Definition 17.4. FPCTL: C2 Flash Programming Control . . . . . . . . . . . . 174
C2 Register Definition 17.5. FPDAT: C2 Flash Programming Data . . . . . . . . . . . . . . 174
12 Rev. 2.9

12 Page





SeitenGesamt 30 Seiten
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