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G1-266P-85-1.8 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer G1-266P-85-1.8
Beschreibung Processor Series Low Power Integrated x86 Solution
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 70 Seiten
G1-266P-85-1.8 Datasheet, Funktion
April 2000
Geode™ GX1 Processor Series
Low Power Integrated x86 Solution
General Description
The National Semiconductor® Geode™ GX1 processor
series is a line of integrated processors specifically
designed to power information appliances for entertain-
ment, education, and business. Serving the needs of con-
www.DataSheet4Ussuo.cmluomteiorsn
and business professionals alike, it’s the perfect
for IA (information appliance) applications such as
thin clients, interactive set-top boxes, and personal internet
access devices.
The Geode GX1 processor series is divided into three main
categories as defined by the core operating voltage. Avail-
able with core voltages of 2.0V, 1.8V, and 1.6V, it offers
extremely low typical power consumption (1.2W, 1.0W, and
0.8W, respectively) leading to longer battery life and
enabling small form-factor, fanless designs. Typical power
consumption is defined as an average, measured running
Microsoft Windows at 80% Active Idle (Suspend-on-Halt)
with a display resolution of 800x600x8 bpp at 75 Hz.
Geode™ GX1 Processor Internal Block Diagram
SYSCLK
Clock Module
SYSCLK
multiplied
by “A”
Core
Clocks
X-Bus
Clocks
16 KB
Unified L1
Cache
(128)
C-Bus (64)
x86 Compatible Core
Integer
TLB Unit
Instruction
Fetch
MMU
Load/Store
INT/NMI
Interrupt
Control
FP_Error
Floating Point
Unit
INTR
IRQ13
SMI#
SUSP#
SUSPA#
Power
Management
Control
Core Suspend
Core Acknowledge
X-Bus Suspend
X-Bus Acknowledge
X-Bus (32)
Arbiter
Write
Buffers
X-Bus
Controller
Read
Buffers
Arbiter
PCI Host
Controller
2D Accelerator
VGA
BLT Engine
ROP Unit
X-Bus CLK
divide by “B”
Display Controller
Compression Buffer
Palette RAM
Timing Generator
3
REQ/GNT
Pairs
PCI
Bus
4
SDRAM
Clocks
64-bit
SDRAM
RGB
YUV
Geode™ Graphics
Companion Interface
National Semiconductor and Virtual System Architecture are registered trademarks of National Semiconductor Corporation.
Geode, WebPAD, and VSA, are trademarks of National Semiconductor Corporation.
For a complete listing of National Semiconductor trademarks, please visit www.national.com/trademarks.
© 2000 National Semiconductor Corporation
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G1-266P-85-1.8 Datasheet, Funktion
Table of Contents (Continued)
4.0 Integrated Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.1
4.2
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4.3
4.4
INTEGRATED FUNCTIONS PROGRAMMING INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.1.1 Graphics Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.1.2 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.1.3 Graphics Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.1.4 Scratchpad RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.1.4.1 Initialization of Scratchpad RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.1.4.2 Scratchpad RAM Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.1.4.3 BLT Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.1.5 Display Driver Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.1.6 CPU_READ/CPU_WRITE Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
INTERNAL BUS INTERFACE UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.2.1 FPU Error Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.2.2 A20M Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.2.3 SMI Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.2.4 640 KB to 1 MB Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.2.5 Internal Bus Interface Unit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
MEMORY CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.3.1 Memory Array Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
4.3.2 Memory Organizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
4.3.3 SDRAM Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
4.3.3.1 SDRAM Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
4.3.4 Memory Controller Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
4.3.5 Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.3.5.1 High Order Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.3.5.2 Auto Low Order Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.3.5.3 Physical Address to DRAM Address Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.3.6 Memory Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
4.3.7 SDRAM Interface Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
GRAPHICS PIPELINE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
4.4.1 BitBLT/Vector Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
4.4.2 Master/Slave Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
4.4.3 Pattern Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
4.4.3.1 Monochrome Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
4.4.3.2 Dither Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
4.4.3.3 Color Patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
4.4.4 Source Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
4.4.5 Raster Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
4.4.6 Graphics Pipeline Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
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G1-266P-85-1.8 pdf, datenblatt
Architecture Overview (Continued)
1.6 INTEGRATED FUNCTIONS
The GX1 processor integrates the following functions tradi-
tionally implemented using external devices:
High-performance 2D graphics accelerator
Separate CRT and TFT control from the display
controller
SDRAM memory controller
PCI bridge
The processor has also been enhanced to support VSA
technology implementation.
The GX1 processor implements a Unified Memory Archi-
www.DataSheet4Ute.ccotumre (UMA). By using DCT (Display Compression Tech-
nology) architecture, the performance degradation inherent
in traditional UMA systems is eliminated.
1.6.1 Graphics Accelerator
The graphics accelerator is a full-featured GUI accelerator.
The graphics pipeline implements a bitBLT engine for
frame buffer bitBLTs and rectangular fills. Additional
instructions in the integer unit may be processed, as the
bitBLT engine assists the CPU in the bitBLT operations that
take place between system memory and the frame buffer.
This combination of hardware and software is used by the
display driver to provide very fast bidirectional transfers
between system memory and the frame buffer. The bitBLT
engine also draws randomly oriented vectors, and scan-
lines for polygon fill. All of the pipeline operations described
in the following list can be applied to any bitBLT operation.
• Pattern Memory: Render with 8x8 dither, 8x8 mono-
chrome, or 8x1 color pattern.
• Color Expansion: Expand monochrome bitmaps to full
depth 8- or 16-bit colors.
• Transparency: Suppresses drawing of background
pixels for transparent text.
• Raster Operations: Boolean operation combines
source, destination, and pattern bitmaps.
1.6.2 Display Controller
The display port is a direct interface to the Geode I/O com-
panion (i.e., CS5530) which drives a TFT flat panel display,
LCD panel, or a CRT display.
The display controller (video generator) retrieves image
data from the frame buffer, performs a color-look-up if
required, inserts the cursor overlay into the pixel stream,
generates display timing, and formats the pixel data for out-
put to a variety of display devices. The display controller
contains DCT architecture that allows the GX1 processor
to refresh the display from a compressed copy of the frame
buffer. DCT architecture typically decreases the screen
refresh bandwidth requirement by a factor of 15 to 20, min-
imizing bandwidth contention.
1.6.3 XpressRAM Memory Subsystem
The memory controller drives a 64-bit SDRAM port directly.
The SDRAM memory array contains both the main system
memory and the graphics frame buffer. Up to four module
banks of SDRAM are supported. Each module bank can
have two or four component banks depending on the mem-
ory size and organization. The maximum configuration is
four module banks with four component banks, each pro-
viding a total of 16 open banks. The maximum memory
size is 512 MB.
The memory controller handles multiple requests for mem-
ory data from the GX1 processor, the graphics accelerator
and the display controller. The memory controller contains
extensive buffering logic that helps minimize contention for
memory bandwidth between graphics and CPU requests.
The memory controller cooperates with the internal bus
controller to determine the cacheability of all memory refer-
ences.
1.6.4 PCI Controller
The GX1 processor incorporates a full-function PCI inter-
face module that includes the PCI arbiter. All accesses to
external I/O devices are sent over the PCI bus, although
most memory accesses are serviced by the SDRAM con-
troller. The internal bus interface unit contains address
mapping logic that determines if memory accesses are tar-
geted for the SDRAM or for the PCI bus. The PCI bus in a
GX1 based system is 3.3 volt only. Do not connect 5 volt
devices on this bus.
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