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Teilenummer | DEM128064A_FGH-P |
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Beschreibung | LCD MODULE | |
Hersteller | Display Elektronik | |
Logo | ||
Gesamt 16 Seiten DISPLAY Elektronik GmbH
LCD MODULE
DEM 128064A FGH-P(RGB)
Product Specification
Version: 2.1.2
07/Nov/2008
DEM 128064A FGH-P(RGB)
4. BLOCK DIAGRAM
Product Specification
DB0~DB7
RS, R/W, E
RSTB
CS2
8
3
CS1
VSS
VDD
V0
VOUT
LED POWER
5
COMMON
DRIVER IC
SBN6400
SEGMENT
DRIVER IC
SBN0064
SEGMENT
DRIVER IC
SBN0064
Seg1~Seg64
Seg65~Seg128
Com1~Com64
LCD PANEL
128 × 64 DOTS
DC/DC Converter
NJU7670M
LED BACK LIGHT
5. PIN ASSIGNMENT
Pin No.
1
2
3
4
Symbol
VSS
VDD
V0
RS
5 R/W
6E
7 DB0
8 DB1
9 DB2
10 DB3
11 DB4
12 DB5
13 DB6
14 DB7
15 CS1
16 CS2
17 RSTB
18 VOUT
19 LED+(A)
20 LED-(B)
21 LED-(G)
22 LED-(R)
Version:2.1.2
Function
Ground
Power supply voltage for logic, + 5.0V.
Input voltage for LCD
Register select RS = 0…Instruction register
Read /Write R/W = 1…Read
Chip enable signal
Data bit 0
Data bit 1
Data bit 2
Data bit 3
Data bit 4
Data bit 5
Data bit 6
Data bit 7
Chip select signal for SBN0064 (1)
Chip select signal for SBN0064 (2)
Reset signal
Output voltage for LCD,-9.5V
LED anode
Blue ,power supply
Green ,power supply
Red ,power supply
RS = 1…Data register
R/W = 0…Write
PAGE: 4
6 Page DEM 128064A FGH-P-(RGB)
Product Specification
11. OPERATING PRINCIPLES & METHODS
11-1. I/O Buffer
Input buffer controls the status between the enable the and disable of chip. Unless the CS1 to CS2 is in active mode. Input
or output of data and instruction does not execute. Therefore internal stade is not change.
Bust RSTB and ADC can operate regardless CS1-CS2.
11-2. Input register
Input register is provided to interface with MPU which is different operating frequency. Input register stores the data
temporarily before writing it into display RAM. When CS1 to CS2 are in the active mode, R/W and RS select the input
register. The data from MPU is written into input register. Then Writing it into display RAM. Data latched for the E signal
and write automatically into the display data RAM by internal operation.
11-3. Output register
Output register stores the data temporarily from display data RAM when CS1 and CS2 are in active mode and R/W and
RS=H, stored data in display data RAM is latched in output register. When CS1 to CS2 are in the active mode and R/W=H,
RS=L, status data (busy check) can read out. To read the contents of display data RAM, twice access of read instruction
needed. In first access, data in display data RAM is latched into output register. In second access, MPU can read data
which is latched. That is , to read the data in display data RAM, it needs dummy read. But staus read is not read needed
dummy.
RS R/W Function
L
L Instruction
H Status read (busy check)
L Data write (from input read register to display data RAM
H
H Data read (from display data RAM to output register)
11-4. Reset
The system can be initialized by setting RSTB terminal at low level when turning power on receiving instruction from
RAM. When RSTB becomes low, following procedure is occurred.
1. Display off
2. Display start line register become set by 0. (Z-address 0)
While RSTB is low, No instruction except status read can be accepted. Therefore, execute other instructions after making
sure than DB4=0 (clear RSTB) and DB7=0 (ready) by status read instruction.
The conditions of power supply data initial power up are shown in table 1.
Table 1. Power Supply Initial Conditions
Item
Symb
Min.
Typ.
Max.
Unit
Reset time
TRS
1
- - us
Rise time
tR
- - 200 us
VDD
RSTB
Version: 2.1.2
4.5[V]
tRS
Figure 7.0
tR
0.7VDD
0.3VDD
PAGE: 10
12 Page | ||
Seiten | Gesamt 16 Seiten | |
PDF Download | [ DEM128064A_FGH-P Schematic.PDF ] |
Teilenummer | Beschreibung | Hersteller |
DEM128064A-FGH-P | LCD MODULE | Display Elektronik |
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