R5F56317DGFC Datasheet PDF - Renesas
Part Number | R5F56317DGFC | |
Description | 100-MHz 32-bit RX MCU | |
Manufacturers | Renesas | |
Logo | ||
There is a preview and R5F56317DGFC download ( pdf file ) link at the bottom of this page. Total 30 Pages |
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RX63N Group, RX631 Group
Renesas MCUs
R01DS0098EJ0180
100-MHz 32-bit RX MCU, on-chip FPU, 165 DMIPS, up to 2-MB flash
memory, various communications interfaces including Ethernet MAC,
Rev.1.80
May 13, 2014
full-speed USB 2.0 host/function/OTG interface, CAN, 10- & 12-bit A/D
converters, RTC
Features
RX63N Group products incorporate an Ethernet controller while
RX631 Group products do not.
■ 32-bit RX CPU core
Max. operating frequency: 100 MHz
Capable of 165 DMIPS in operation at 100 MHz
Single precision 32-bit IEEE-754 floating point
Two types of multiply-and-accumulation unit (between memories and
between registers)
32-bit multiplier (fastest instruction execution takes one CPU clock cycle)
Divider (fastest instruction execution takes two CPU clock cycles)
Fast interrupt
CISC Harvard architecture with 5-stage pipeline
Variable-length instructions: Ultra-compact code
Supports the memory protection unit (MPU)
JTAG and FINE (two-line) debugging interfaces
■ Low-power design and architecture
Operation from a single 2.7- to 3.6-V supply
Low power consumption: A product that supports all peripheral functions
draws only 500 μA/MHz.
RTC is capable of operation from a dedicated power supply (min. operating
voltage: 2.3 V).
Four low-power modes
■ On-chip main flash memory, no wait states
Supports ROM-less versions and versions with up to 2 Mbytes of ROM
(ROMless/256 Kbytes/384 Kbytes/512 Kbytes: RX631 Group only)
100-MHz operation, 10-ns read cycle (no wait states)
768-Kbyte to 2-Mbyte capacities
User code is programmable by on-board or off-board programming
■ On-chip data flash memory
ROM-less or 32 Kbytes of ROM (reprogrammable up to 100,000 times)
Programming/erasing as background operations (BGOs)
■ On-chip SRAM, no wait states
64 Kbytes/128 Kbytes/192 Kbytes/256 Kbytes of SRAM
For instructions and operands
Can provide backup on deep software standby
■ DMA
DMAC: Four channels
DTC
EXDMAC: Two channels
Dedicated DMAC for the Ethernet controller: Single channel
■ Reset and supply management
Power-on reset (POR)
Low voltage detection (LVD) with voltage settings
■ Clock functions
External crystal oscillator or internal PLL for operation at 4 to 16 MHz
Internal 125-kHz LOCO and 50-MHz HOCO
125-kHz clocks for the IWDT
■ Real-time clock
Adjustment functions (30 seconds, leap year, and error)
Time capture function
(for capturing times in response to event-signal input on external pins)
■ Independent watchdog timer
125-kHz LOCO clock operation
■ Useful functions for IEC60730 compliance
Oscillation-stoppage detection, frequency measurement, CRC, IWDT, self-
diagnostic function for the A/D converter, etc.
PLQP0176KB-A 24 × 24 mm, 0.5-mm pitch
PLQP0144KA-A 20 × 20 mm, 0.5-mm pitch
PLQP0100KB-A 14 × 14 mm, 0.5-mm pitch
PLQP0064KB-A 10 × 10 mm, 0.5-mm pitch
PLQP0048KB-A 7 × 7 mm, 0.5-mm pitch
PTLG0177KA-A 8 × 8 mm, 0.5-mm pitch
PTLG0145KA-A 7 × 7 mm, 0.5-mm pitch
PTLG0100JA-A 7 × 7 mm, 0.65-mm pitch
PTLG0064JA-A 6 × 6 mm, 0.65-mm pitch
PLBG0176GA-A 13 × 13mm, 0.8-mm pitch
■ Various communications interfaces
Ethernet MAC (1) (not in RX631 Group products)
Host/function or OTG controller (1) and function controller (1) with full-
speed USB 2.0 transfer
CAN (compliant with ISO11898-1), incorporating 32 mailboxes (up to 3
modules)
SCI with multiple functionalities (up to 13)
Choose from among asynchronous mode, clock-synchronous mode, smart-
card interface mode, simplified SPI, simplified I2C, and extended serial
mode.
I2C bus interface for transfer at up to 1 Mbps (up to 4)
RSPI for high-speed transfer (up to 3)
Parallel data capture unit (PDC) (1) (available for 512 Kbytes/384 Kbytes/
256 Kbytes flash memory with 177-pin, 176-pin, 145-pin, and 144-pin)
■ External address space
Buses for high-speed data transfer (max. operating frequency of 50 MHz)
8 CS areas (8 × 16 Mbytes)
Multiplexed bus or separate bus are selectable per area.
8-, 16-, or 32-bit bus space is selectable per area
Independent SDRAM area (128 Mbytes)
■ Up to 20 extended-function timers
16-bit MTU2: input capture, output compare, PWM waveform output,
phase-counting mode (6 channels)
16-bit TPU: input capture, output compare, phase-counting mode (12
channels)
8-bit TMR (4 channels)
16-bit compare-match timers (4 channels)
■ A/D converter for 1-MHz Operation
Up to 21 × 12-bit channels, and incorporating 1 sample-and-hold circuit
Up to 8 × 10-bit channels, and incorporating 1 sample-and-hold circuit
Addition of results of A/D conversion (in the 12-bit converter)
Self diagnosis (for the 10-bit converter)
■ 10-bit D/A converter: 2 channels
■ Temperature sensor for measuring temperature within
the chip
■DEU
AES encryption and decryption functions
128/192/256-bit key length
ECB/CBC mode
■ Register write protection can protect values in
important registers against overwriting.
■ Up to 134 pins for general I/O ports
5-V tolerance, open drain, input pull-up, switchable driving ability
■ Unique ID
16-byte ID code is provided for each chip (only for the G version)
■ Operating temp. range
D version: -40 to +85°C
G version: -40 to +105°C
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 1 of 208
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RX63N Group, RX631 Group
1. Overview
Table 1.1
Outline of Specifications (4/6)
Classification
Timers
Module/Function
Description
16-bit timer pulse unit
(TPUa)
(16 bits x 6 channels) x 2 unit
Maximum of 16 pulse-input/output possible
Select from among seven or eight counter-input clock signals for each channel
Input capture/output compare function
Output of PWM waveforms in up to 15 phases in PWM mode
Buffered operation and phase-counting mode (two phase encoder input) depending on
the channel
Support for cascade-connected operation (32 bits x 2 channels)
PPG output trigger can be generated
Capable of generating conversion start triggers for the A/D converters
Signals from the input capture pins are input via a digital filter
Clock frequency measuring method
Multi-function timer
pulse unit 2 (MTU2a)
(16 bits x 6 channels) x 1 unit
Time bases for the 6 × 16-bit timer channels can be provided via up to sixteen pulse-input/
output lines and three pulse-input lines
Select from among eight counter-input clock signals for each channel (PCLK/1, PCLK/4,
PCLK/16, PCLK/64, MTCLKA, MTCLKB, MTCLKC, MTCLKD) other than channel 5, for
which only four signals are available.
Input capture function
21 output compare/input capture registers
Complementary PWM output mode
Reset synchronous PWM mode
Phase-counting mode
Generation of triggers for A/D converter conversion
Digital filter
Signals from the input capture pins are input via a digital filter
PPG output trigger can be generated
Clock frequency measuring function
Frequency measuring The MTU or unit 0 TPU module can be used to monitor the main clock, subclock,
method (MCK)
HOCO clock, LOCO clock, and PLL clock for abnormal frequencies.
Port output enable 2 Controls the high-impedance state of the MTU’s waveform output pins
(POE2a)
Programmable pulse
generator (PPG)
(4 bits x 4 groups) x 2 units
Pulse output with the MTU2 or TPU output as a trigger
Maximum of 32 pulse-output possible
8-bit timers (TMR)
(8 bits x 2 channels) x 2 units
Select from among seven internal clock signals (PCLK/1, PCLK/2, PCLK/8, PCLK/32,
PCLK/64, PCLK/1024, PCLK/8192) and one external clock signal
Capable of output of pulse trains with desired duty cycles or of PWM signals
The 2 channels of each unit can be cascaded to create a 16-bit timer
Generation of triggers for A/D converter conversion
Capable of generating baud-rate clocks for SCI5, SCI6, and SCI12
Compare match timer (16 bits x 2 channels) x 2 units
(CMT)
Select from among four internal clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512)
Realtime clock
(RTCa)
Clock sources: Main clock, subclock
Clock and calendar functions
Interrupt sources: Alarm interrupt, periodic interrupt, and carry interrupt
Battery backup operation
Time-capture facility for three values
Watchdog timer
(WDTA)
14 bits x 1 channel
Select from among 6 counter-input clock signals (PCLK/4, PCLK/64, PCLK/128, PCLK/
512, PCLK/2048, PCLK/8192)
Independent
watchdog timer
(IWDTa)
14 bits x 1 channel
Counter-input clock: IWDT-dedicated on-chip oscillator
Dedicated clock/1, dedicated clock/16, dedicated clock/32, dedicated clock/64, dedicated
clock/128, dedicated clock/256
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 5 of 208
Preview 5 Page |
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