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Número de pieza | FZL4146 | |
Descripción | Quad Driver Incl. Short-Circuit Signaling | |
Fabricantes | Siemens Semiconductor Group | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de FZL4146 (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
No Preview Available ! Quad Driver Incl. Short-Circuit Signaling
Bipolar IC
Features
q Short-circuit signaling
q Four driver circuits for driving power transistors
q Turn-ON threshold setting from 1.5 to 7 V
FZL 4146
P-DSO-20-7
Type
FZL 4146 G
Ordering Code
Q67000-H8743
Package
P-DSO-20-7 (SMD)
General Description
The IC comprises four driver circuits capable of driving power transistors (PNP or
PMOS). The output transistors are protected against short-circuit to ground and supply
voltage. The turn-ON threshold can be set from 1.5 V to 7 V. Overload at one or several
outputs will be indicated at pin SQ (signaling output). The corresponding power
transistors are then protected by changeover to clock-governed operation.
Circuit Description
Each driver circuit has one active high driver input Dl and a common enable input ENA
(active high) is provided for all stages. The Q output is designed to drive the output
transistors. The load current is sampled and, if necessary, limited via pin W. If the load
current exceeds the preset value, the output stage switches off. Switching-ON again is
provided by the built-in clock generator T. Its operation requires an external capacitor Ce
at pin CE. If Ce is bridged by a break-key, switching-ON can only be carried out by
operating this key. The duty cycle of the clock generator is 1:47 (e.g. 45 µs/2.1 ms with
Ce = 10 nF). The clock generator is privileged versus the current sensor shut down.
When the supply is connected, the internal RS-FF goes into the state corresponding to
the released output.
Semiconductor Group
1
03.96
1 page FZL 4146
Block Diagram
Semiconductor Group
5
5 Page FZL 4146
Characteristics (cont’d)
Supply voltage 4.5 V ≤ VS ≤ 40 V, junction temperature – 25 °C ≤ Tj ≤ 125 °C
Parameter
Symbol Limit Values Unit Test Condition
min. typ. max.
Difference between
VTS and input
switching
threshold ENA, DI
during transition
from L to H
VDIH –
VTS
– 0.2
0.2 V 2 V ≤ VTS ≤ 4.8 V
Idling voltage at VQH VS – VS – VS – V VS ≥ 18 V
output Q
13 11.5 10
VS turn-Off threshold VTSV
Resistance
across Q and VS
RQ
Z-diode
internal resistance
RZ
2.5 4.5 V VQ > VQL;
IQ = – 20 µA
8 13 19 kΩ VENA = 0 V;
IQ = – 100 µA
RQ = (VS – VQ)/0.1 mA
20 50 Ω VENA = 0 V;
IQ1 = – 3 mA
IQ2 = – 8 mA,
RQ = ∆VQ/5 mA
Footnotes for the Characteristics
1) The given limit values apply to inputs Dl, ENA, if they are not measured, from 0 to 40 V.
2) The layout provides an adaption of Vwtyp. from VS – 0.3 V to VS – 0.4 V or VS – 0.48 V by simply
changing of the ALU mask.
3) All inputs Dl1 to Dl4 and W1 to W4 as well as Q1 to Q4
ISON means the sum of all currents flowing from the voltage source VS into the IC, i.e.
ISON = IS + Σ IDI + Σ IENA + Σ IW + Σ IQ.
4) All other pins are open.
5) The delay time of loop W → I regulator → RS-FF → AND → current source → Q is
unaccessable for measurement without external wiring due to fast reaction of the current
regulator. For this reason, in case of overload, the above mentioned switch-OFF delay time is
replaced by the delay time for input W → output SQ.
Measurement: jump function at W from VW = VS to VW = VS – 1 V
6) IQ = leakage current ICBO of the external PNP-driver transistor
7) For VDI, TS < 1.5 V, IDl, ENA remains below its minimum value; it is however ensured that in case of
open inputs the corresponding outputs will be safely disabled.
Semiconductor Group
11
11 Page |
Páginas | Total 14 Páginas | |
PDF Descargar | [ Datasheet FZL4146.PDF ] |
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