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ACPL-P314 Schematic ( PDF Datasheet ) - Avago Technologies

Teilenummer ACPL-P314
Beschreibung 0.6 Amp Output Current IGBT Gate Driver Optocoupler
Hersteller Avago Technologies
Logo Avago Technologies Logo 




Gesamt 13 Seiten
ACPL-P314 Datasheet, Funktion
ACPL-P314 and ACPL-W314
0.6 Amp Output Current IGBT Gate Driver Optocoupler
Data Sheet
Description
The ACPL-P314/W314 consists of a GaAsP LED optically
coupled to an integrated circuit with a power output
stage. These optocouplers are ideally suited for driving
power IGBTs and MOSFETs used in motor control
inverter applications. The high operating voltage range
of the output stage provides the drive voltages
required by gate controlled devices. The voltage and
current supplied by this optocoupler makes it ideally
suited for directly driving small or medium power
IGBTs.
Functional Diagram
ANODE 1
N.C. 2
CATHODE 3
SHIELD
6 VCC
5 VO
4 VEE
Truth Table
LED VO
OFF LOW
ON HIGH
Note: A 0.1 µF bypass capacitor
must be connected between
pins VCC and VEE.
Features
High speed response.
Ultra high CMR.
Bootstrappable supply current.
Available in Stretched SO-6 package
Package Clearance/Creepage at 8mm (ACPL-W314)
Safety Approval:
UL Recognized with 3750 Vrms for 1 minute per
UL1577.
CSA Approved.
IEC/EN/DIN EN 60747-5-2 Approved with VIORM =
630VPEAK for option 060.
Specifications
0.6 A maximum peak output current.
0.4 A minimum peak output current.
0.7 µs maximum propagation delay over
temperature range.
ICC(max) = 3 mA maximum supply current.
10 kV/µs minimum common mode rejection (CMR)
at VCM = 1000 V.
Wide VCC operating range: 10 V to 30 V over
temperature range.
Wide operating temperature range: –40°C to 100°C.
Applications
Isolated IGBT/Power MOSFET gate drive
AC and brushless DC motor drives
Industrial inverters
Inverter for home appliances
Induction cooker
Switching Power Supplies (SPS)
CAUTION: It is advised that normal static precautions be taken
in handling and assembly of this component to prevent
damage and/or degradation which may be induced by ESD.






ACPL-P314 Datasheet, Funktion
Table 3. Absolute Maximum Ratings
Parameter
Storage Temperature
Operating Temperature
Average Input Current
Peak Transient Input Current
(<1 µs pulse width, 300pps)
Reverse Input Voltage
"High" Peak Output Current
"Low" Peak Output Current
Supply Voltage
Output Voltage
Output Power Dissipation
Input Power Dissipation
Lead Solder Temperature
Solder Reflow Temperature Profile
Symbol
TS
TA
IF(AVG)
IF(TRAN)
Min.
-55
-40
Max.
125
100
25
1.0
Units
°C
°C
mA
A
VR 5 V
IOH(PEAK)
0.6 A
IOL(PEAK)
0.6 A
VCC - VEE
-0.5
35
V
VO(PEAK)
-0.5
VCC
V
PO 250 mW
PI 45 mW
260°C for 10 sec., 1.6 mm below seating plane
See Package Outline Drawings section
Note
1
2
2
3
4
Table 4. Recommended Operating Conditions
Parameter
Symbol
Power Supply
Input Current (ON)
Input Voltage (OFF)
Operating Temperature
VCC - VEE
IF(ON)
VF(OFF)
TA
Min.
10
8
- 3.0
- 40
Max.
30
12
0.8
100
Units
V
mA
V
°C
Note
Table 5. Electrical Specifications (DC)
Over recommended operating conditions unless otherwise specified.
Parameter
High Level Output Current
Low Level Output Current
High Level Output Voltage
Low Level Output Voltage
High Level Supply Current
Low Level Supply Current
Threshold Input Current
Low to High
Threshold Input Voltage
High to Low
Input Forward Voltage
Temperature Coefficient of
Input Forward Voltage
Input Reverse Breakdown Voltage
Input Capacitance
Symbol
IOH
IOL
VOH
VOL
ICCH
ICCL
IFLH
Min.
0.2
0.4
0.2
0.4
VCC-4
Typ.
0.5
0.4
0.5
VCC-1.8
0.4
0.7
1.2
Max. Units
A
A
A
A
V
1V
3 mA
3 mA
7 mA
VFHL 0.8
V
VF
VF/TA
1.2
1.5
-1.6
1.8 V
mV/°C
BVR 5
CIN 60
V
pF
Test Conditions
VO = VCC - 4
VO = VCC - 10
VO = VEE + 2.5
VO = VEE + 10
IO = -100 mA
IO = 100 mA
IO = 0 mA
IO = 0 mA
IO = 0 mA,
VO > 5 V
IO = 0 mA,
VO > 5 V
IF = 10 mA
IF = 10 mA
IR = 10 µA
f = 1 MHz, VF = 0 V
Fig.
2
3
5
6
1
4
7, 8
7, 8
9, 15
16
Note
5
2
5
2
6, 7
14
14
6

6 Page









ACPL-P314 pdf, datenblatt
LED Drive Circuit Considerations for Ultra High CMR
Performance
Without a detector shield, the dominant cause of
optocoupler CMR failure is capacitive coupling from
the input side of the optocoupler, through the package,
to the detector IC as shown in Figure 21. The ACPL-
P314/W314 improves CMR performance by using a
detector IC with an optically transparent Faraday shield,
which diverts the capacitively coupled current away
from the sensitive IC circuitry. However, this shield does
not eliminate the capacitive coupling between the LED
and optocoupler pins 5-8 as shown in Figure 22. This
capacitive coupling causes perturbations in the LED
current during common mode transients and becomes
the major source of CMR failures for a shielded
optocoupler. The main design objective of a high CMR
LED drive circuit becomes keeping the LED in the
proper state (on or off ) during common mode
transients. For example, the recommended application
circuit (Figure 19), can achieve 10 kV/µs CMR while
minimizing component complexity.
Techniques to keep the LED in the proper state are
discussed in the next two sections.
1 CLEDP
6
25
3 CLEDN
4
Figure 21. Optocoupler Input to Output Capacitance Model for
Unshielded Optocouplers.
1 CLEDP CLED01
6
2 5CLED02
3 CLEDN SHIELD
4
Figure 22. Optocoupler Input to Output Capacitance Model for
Shielded Optocouplers.
CMR with the LED On (CMRH)
A high CMR LED drive circuit must keep the LED on
during common mode transients. This is achieved by
overdriving the LED current beyond the input threshold
so that it is not pulled below the threshold during a
transient. A minimum LED current of 8 mA provides
adequate margin over the maximum IFLH of 5 mA to
achieve 10 kV/µs CMR.
CMR with the LED Off (CMRL)
A high CMR LED drive circuit must keep the LED off (VF
VF(OFF)) during common mode transients. For
example, during a -dVCM/dt transient in Figure 23, the
current flowing through CLEDP also flows through the
RSAT and VSAT of the logic gate. As long as the low
state voltage developed across the logic gate is less
than VF(OFF) the LED will remain off and no common
mode failure will occur.
+5V
+
VSAT
-
1 CLEDP
ILEDP
2
6
0.1 µF
5
3 CLEDN
SHIELD
4
THEARROWS INDICATETHEDIRECTION
OF CURRENTFLOW DURING - dVCM/ dt
+VCC = 18V
- Rg
VCM
+5 V
+
VSAT
-
1 CLEDP
ILEDP
2
6
0.1 µF
5
3 CLEDN SHIELD
4
THE ARROWS INDICATE THE DIRECTION
OF CURRENT FLOW DURING - dVCM/dt
+ VCC = 18V
- Rg
VCM
Figure 23. Equivalent Circuit for Figure 17 During Common Mode
Transient.
The open collector drive circuit, shown in Figure 24,
can not keep the LED off during a +dVCM/dt transient,
since all the current flowing through CLEDN must be
supplied by the LED, and it is not recommended for
applications requiring ultra high CMR1 performance.
The alternative drive circuit which like the
recommended application circuit (Figure 19), does
achieve ultra high CMR performance by shunting the
LED in the off state.
+5 V
1 CLEDP
6
2
CLEDN
3 ILEDN
SHIELD
Q1
5
4
Figure 24. Not Recommended Open Collector Drive Circuit.

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