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CDP1802ACD3 Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer CDP1802ACD3
Beschreibung High-Reliability CMOS 8-Bit Microprocessor
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 27 Seiten
CDP1802ACD3 Datasheet, Funktion
®
Data Sheet
CDP1802AC/3
October 17, 2008
FN1441.3
High-Reliability CMOS 8-Bit
Microprocessor
The CDP1802A/3 High-Reliability LSI CMOS 8-bit register
oriented Central-Processing Unit (CPU) is designed for use
as a general purpose computing or control element in a wide
range of stored-program systems or products.
The CDP1802A/3 includes all of the circuits required for
fetching, interpreting, and executing instructions which have
been stored in standard types of memories. Extensive
input/output (I/O) control features are also provided to
facilitate system design.
The 1800 Series Architecture is designed with emphasis on
the total microcomputer system as an integral entity so that
systems having maximum flexibility and minimum cost can be
realized. The 1800 Series CPU also provides a synchronous
interface to memories and external controllers for I/O devices,
and minimizes the cost of interface controllers. Further, the I/O
interface is capable of supporting devices operating in polled,
interrupt-driven, or direct memory-access modes.
The CDP1802AC/3 is functionally identical to its
predecessor, the CDP1802. The “A” version includes some
performance enhancements and can be used as a direct
replacement in systems using the CDP1802.
This type is supplied in a 40 Ld dual-in-line sidebrazed
ceramic package (D suffix).
Features
For Use In Aerospace, Military, and Critical Industrial
Equipment
• Minimum Instruction Fetch-Execute Time of 4.5µs
(Maximum Clock Frequency of 3.6MHz) at VDD = 5V,
TA = +25°C
• Operation Over the Full Military
Temperature Range . . . . . . . . . . . . . . . -55°C to +125°C
• Any Combination of Standard RAM and ROM Up to
65,536 Bytes
• 8-Bit Parallel Organization With Bi-directional Data
Bus and Multiplexed Address Bus
• 16x16 Matrix of Registers for Use as Multiple Program
Counters, Data Pointers, or Data Registers
• On-Chip DMA, Interrupt, and Flag Inputs
• High Noise Immunity . . . . . . . . . . . . . . . . . . 30% of VDD
• Pb-Free (RoHS compliant)
Ordering Information
PART
NUMBER
PART
MARKING
TEMP. RANGE
(°C)
CLOCK FREQUENCY
AT 5V
PACKAGE
PKG
DWG. #
CDP1802ACD3
CDP1802ACD3
-55 to +125
Up to 3.2MHz
40 Ld SBDIP
D40.6
NOTE: These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible
with both SnPb and Pb-free soldering operations.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2002, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.






CDP1802ACD3 Datasheet, Funktion
CDP1802AC/3
Dynamic Electrical Specifications CL = 50pF, Timing Measurement at 0.5 VDD Point. Parameters with MIN and/or MAX limits are
100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
PARAMETERS
PROGAGATION DELAY TIMES, tPLH, tPHL
Clock to TPA, TPB
VDD (V)
5
-55°C TO +25°C
MIN MAX
- 275
+125°C
MIN MAX
UNITS
- 370 ns
Clock-to-Memory High Address Byte, tPLH, tPHL
Clock-to-Memory Low Address Byte Valid, tPLH, tPHL
Clock to MRD, tPLH, tPHL
Clock to MWR, tPLH, tPHL
Clock to (CPU DATA to BUS) Valid, tPLH, tPHL
Clock to State Code, tPLH, tPHL
Clock to Q, tPLH, tPHL
Clock to N (0 to 2), tPLH, tPHL
INTERFACE TIMING REQUIREMENTS (Note 7)
5 - 725 - 950 ns
5 - 340 - 425 ns
5 - 340 - 425 ns
5 - 275 - 370 ns
5 - 430 - 550 ns
5 - 440 - 550 ns
5 - 375 - 475 ns
5 - 400 - 525 ns
Data Bus Input Setup, tSU
Data Bus Input Hold, tH
DMA Setup, tSU
DMA Hold, tH
Interrupt Setup, tSU
Interrupt Hold, tH
WAIT Setup, tSU
EF1-4 Setup, tSU
EF1-4 Hold, tH
REQUIRED PULSE WIDTH TIMES
5 10 - 10 - ns
5
175
-
230 -
ns
5 10 - 10 - ns
5
200
-
270 -
ns
5 10 - 10 - ns
5
175
-
230 -
ns
5 30 - 30 - ns
5 20 - 20 - ns
5
100
-
135 -
ns
CLEAR Pulse Width, tWL
5
CLOCK Pulse Width, tWL
5
NOTE:
7. Minimum input setup and hold times required by Part CDP1802AC/3.
150
-
200 -
ns
140
-
185 -
ns
6 FN1441.3
October 17, 2008

6 Page









CDP1802ACD3 pdf, datenblatt
CDP1802AC/3
Machine Cycle Timing Waveforms (Propagation Delays Not Shown) (Continued)
0 1 2 3 4 56 7 0 12 3 4 5 6 7 01 2 34 5 6 7
CLOCK
TPA
TPB
MACHINE
CYCLE
INSTRUCTION
CYCLE n
FETCH (S0)
CYCLE (n+1)
EXECUTE (S1)
CYCLE (n+2)
DMA (S2)
DMA-IN
MRD
MWR
MEMORY
OUTPUT
DATA BUS
(NOTE)
MEMORY READ CYCLE
VALID OUTPUT
MEMORY READ, WRITE
OR NON-MEMORY CYCLE
VALID DATA FROM INPUT DEVICE
MEMORY WRITE CYCLE
NOTE: USER GENERATED SIGNAL
“DON’T CARE” OR INTERNAL DELAYS
HIGH IMPEDANCE STATE
FIGURE 10. DMA IN CYCLE TIMING WAVEFORMS
01234567012345670123456
CLOCK
TPA
TPB
MACHINE
CYCLE
CYCLE n
CYCLE (n + 1)
CYCLE (n + 2)
INSTRUCTION
FETCH (S0)
EXECUTE (S1)
DMA (S2)
DMA OUT
(NOTE)
MRD
MWR
MEMORY
OUTPUT
DATA
STROBE
(S2 ² TPB)
(NOTE)
MEMORY READ CYCLE
NOTE: USER GENERATED SIGNAL
VALID OUTPUT
VALID DATA FROM MEMORY
MEMORY READ, WRITE
OR NON-MEMORY CYCLE
“DON’T CARE” OR INTERNAL DELAYS
MEMORY READ CYCLE
HIGH IMPEDANCE STATE
FIGURE 11. DMA OUT CYCLE TIMING WAVEFORMS
12 FN1441.3
October 17, 2008

12 Page





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