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GD25Q16B Schematic ( PDF Datasheet ) - ELM

Teilenummer GD25Q16B
Beschreibung Uniform sector dual and quad serial flash
Hersteller ELM
Logo ELM Logo 




Gesamt 30 Seiten
GD25Q16B Datasheet, Funktion
GD25Q16B
DATASHEET
48 - 1
Rev.1.1






GD25Q16B Datasheet, Funktion
Uniform Sector
Dual and Quad Serial Flash
GD25Q16B
HOLD# (IGO3)D25I/QO 16BxIGx UHonldifInopurtm(DastaeIncptuot Orutdpuut 3a)l and quad serial flash
VCC
Power Supply
BLOCK DIAGRAM
WP#(IO2)
Write Control
Logic
HOLD#(IO3)
SCLK
CS#
SI(IO0)
SO(IO1)
SPI
Command &
Control Logic
Status
Register
High Voltage
Generators
Flash
Memory
Page Address
Latch/Counter
Column Decode And
256-Byte Page Buffer
Byte Address
Latch/Counter
6
48 - 6
Rev.1.1

6 Page









GD25Q16B pdf, datenblatt
GD25Q16BxIGx Uniform sector dual and quad serial flash
Uniform Sector
Dual and Quad Serial Flash
GD25Q16B
QE bit.
The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation. When
the QE bit is set to 0 (Default) the WP# pin and HOLD# pin are enable. When the QE pin is set to 1, the Quad IO2 and IO3
pins are enabled. (The QE bit should never be set to 1 during standard SPI or Dual SPI operation if the WP# or HOLD#
pins are tied directly to the power supply or ground)
LB bit.
The LB bit is a non-volatile One Time Program (OTP) bit in Status Register (S10) that provide the write protect control
and status to the Security Registers. The default state of LB is 0, the security registers are unlocked. LB can be set to 1
individually using the Write Register instruction. LB is One Time Programmable, once it’s set to 1, the Security Registers
will become read-only permanently.
CMP bit
The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction the BP4-BP0 bits to
provide more flexibility for the array protection. Please see the Status registers Memory Protection table for details. The
default setting is CMP=0.
SUS bit
The SUS bit is a read only bit in the status register (S15 ) that is set to 1 after executing an Erase/Program Suspend
(75H) command. The SUS bit is cleared to 0 by Erase/Program Resume (7AH) command as well as a power-down,
power-up cycle.
4812- 12
Rev.1.1

12 Page





SeitenGesamt 30 Seiten
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