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R5F562TAEDFF Schematic ( PDF Datasheet ) - Renesas

Teilenummer R5F562TAEDFF
Beschreibung 100-MHz 32-bit RX MCUs
Hersteller Renesas
Logo Renesas Logo 




Gesamt 30 Seiten
R5F562TAEDFF Datasheet, Funktion
DATASHEET
RX62T Group, RX62G Group
Renesas MCUs
R01DS0096EJ0200
100-MHz 32-bit RX MCUs, FPU, 165 DMIPS, 12-bit ADC (3 S/H circuits, double data
register, amplifier, comparator): two units, 10-bit ADC one unit, the three ADC units are
Rev.2.00
Jan 10, 2014
capable of simultaneous 7-ch. sampling, 100-MHz PWM (two three-phase complementary
channels and four single-phase complementary channels or three three-phase
complementary channels and one single-phase complementary channel)
Features
32-bit RX CPU core
Max. operating frequency: 100 MHz
Capable of 165 DMIPS in operation at 100 MHz
Single precision 32-bit IEEE-754 floating point
Accumulator handles 64-bit results (for a single
instruction) from 32- × 32-bit operations
Multiplication and division unit handles 32- × 32-bit
operations (multiplication instructions take one CPU
clock cycle)
Fast interrupt
Divider (fastest instruction execution takes two CPU
clock cycles)
Fast interrupt
CISC Harvard architecture with 5-stage pipeline
Variable-length instructions: Ultra-compact code
Supports the memory protection unit (MPU)
Background JTAG debugging plus high-speed tracing
Operating voltage
Single 3.3- or 5-V supply; 5-V analog supply is possible
with 3.3-V products
Low-power design and architecture
Four low-power modes
On-chip main flash memory, no wait states
100-MHz operation, 10-ns read cycle
No wait states for reading at full CPU speed
64-Kbyte/128-Kbyte/256-Kbyte capacities
For instructions and operands
User code programmable via the SCI or JTAG
On-chip data flash memory
Max. 32 Kbytes, reprogrammable up to 30,000 times
Erasing and programming impose no load on the CPU.
On-chip SRAM, no wait states
8-Kbyte/16-Kbyte SRAM
For instructions and operands
DMA
DTC: The single unit is capable of transfer on multiple
channels
Reset and supply management
Power-on reset (POR)
Low voltage detection (LVD) with voltage settings
Clock functions
External crystal oscillator or internal PLL for operation at
8 to 12.5 MHz
Internal 125-kHz LOCO for the IWDT
Detection of main oscillator stoppage (for IEC 60730
compliance)
Independent watchdog timer
(for IEC60730compliance)
125-kHz LOCO clock operation
Software is incapable of stopping the robust WDT.
R01DS0096EJ0200 Rev.2.00
Jan 10, 2014
PLQP0112JA-A 20×20mm, 0.65mm pitch
PLQP0100KB-A 14×14mm, 0.5mm pitch
PLQP0080JA-A 14×14mm, 0.65mm pitch
PLQP0064KB-A 10×10mm, 0.5mm pitch
PLQP0064GA-A 14x14 mm, 0.8mm pitch
Up to 7 communications interfaces
1: CAN (compliant with ISO11898-1), incorporating 32
mailboxes
3: SCIs, with asynchronous mode (incorporating noise
cancellation), clock-synchronous mode, and smart-card
interface mode
1: I2C bus interface, capable of SMBus operation
1: RSPI
1: LIN
Up to 16 16-bit timers
8: 16-bit MTU3: 100-MHz operation, input capture,
output compare, two three-phase complementary PWM
output channels, complementary PWM imposing no load
on the CPU, phase-counting mode
4: 16-bit GPT: 100-MHz operation, input capture, output
compare, four complementary single-phase PWM output
channels, or one three-phase complementary PWM
output channel and one single-phase complementary
PWM output channel, complementary PWM imposing no
load on the CPU, operation linked with comparator (for
counting and control of PWM-signal negation), detection
of abnormal oscillation frequencies (for IEC 60730
compliance)
4: 16-bit CMT
Generation of delays in PWM waveforms (only for
the RX62G Group)
The timing with which signals on the 16-bit GPT PWM
output pin rise and fall can be controlled with an accuracy
of up to 312 ps (in operation at 100 MHz).
Three A/D converter units for 1-MHz operation,
for a total of 20 channels
Three units are capable of simultaneous sampling on
seven channels
Self diagnosis (for IEC60730 compliance)
8: Two 12-bit ADC units: three sample-and-hold circuits,
double data registers, amplifier, comparator
12: Single 10-bit ADC unit
CRC (cyclic redundancy check) calculation unit
Monitoring of data being transferred (for IEC 60730
compliance)
Monitoring of data in memory (for IEC 60730
compliance)
Up to 61 input–output ports and up to 21 input-only
ports
PORT registers: Monitoring of output ports (for IEC
60730 compliance)
Operating temp. range
–40C to +85C
–40C to +105C
Page 1 of 134






R5F562TAEDFF Datasheet, Funktion
Under development Preliminary document
Specifications in this document are tentative and subject to change.
RX62T Group, RX62G Group
1. Overview
Table 1.1
Outline of Specifications (5 / 5)
Classification Module/Function
Description
A/D converter
10-bit A/D converter
(ADA)
10 bits (1 unit x 12 channels)
10-bit resolution
Conversion time:
1.0 s per channel (in operation with A/D conversion clock ADCLK at 50 MHz) for
AVCC0 = 4.0 to 5.5 V
2.0 s per channel (in operation with A/D conversion clock ADCLK at 25 MHz) for AVCC
= 3.0 to 3.6 V
Two basic operating modes
Single mode and scan mode
Scan mode
One-cycle scan mode
Continuous scan mode
Sample-and-hold function
A common sample-and-hold circuit for both units is included.
A/D-conversion register settings for each input pin
Three ways to start A/D conversion
Conversion can be started by software, a conversion start trigger from a timer (MTU3 or
GPT), or an external trigger signal.
Functionality for 8-bit precision output
Right-shifting the results of conversion for output by two bits is selectable.
Self-diagnostic function
The self-diagnostic function internally generates three analog input voltages (AVSS,
VREF x 1/2, VREF).
CRC calculator (CRC)
CRC code generation for arbitrary amounts of data in 8-bit units
Select any of three generating polynomials:
X8 + X2 + X + 1, X16 + X15 + X2 + 1, or X16 + X12 + X5 + 1.
Generation of CRC codes for use with LSB-first or MSB-first communications is
selectable.
Operating frequency
ICLK: 8 to 100 MHz
PCLK: 8 to 50 MHz
Power supply voltage
3-V version
VCC = PLLVCC = 2.7 to 3.6V
AVCC0 = AVCC = 3.0 to 3.6V, or 4.0 to 5.5V
VREFH0 = 3.0 to AVCC0, or 4.0 to AVCC0
VREF = 3.0 to AVCC, or 4.0 to AVCC
5-V version
VCC = PLLVCC = 4.0 to 5.5V
AVCC0 = AVCC = 4.0 to 5.5V
VREFH0 = 4.0 to AVCC0
VREF = 4.0 to AVCC
Operating temperature
D version: -40 to +85C, G version: -40 to +105C*1
Packages
112-pin LQFP (PLQP0112JA-A, 20x20-0.65-mm pitch)
100-pin LQFP (PLQP0100KB-A, 14x14-0.5-mm pitch)
80-pin LQFP (PLQP0080JA-A, 14x14-0.65-mm pitch)
64-pin LQFP (PLQP0064KB-A, 10x10-0.5-mm pitch)
64-pin LQFP (PLQP0064GA-A, 14x14-0.8mm pitch)
Note 1. Please contact Renesas Electronics sales office for derating of operation under Ta = +85°C to +105°C. Derating is the
systematic reduction of load for the sake of improved reliability.
R01DS0096EJ0200 Rev.2.00
Jan 10, 2014
Page 6 of 134

6 Page









R5F562TAEDFF pdf, datenblatt
Under development Preliminary document
Specifications in this document are tentative and subject to change.
RX62T Group, RX62G Group
1.3 Block Diagram
Figure 1.2 shows a block diagram.
1. Overview
ROM
RAM
RX CPU
MPU
Clock
generation
circuit
POR
LVD
MTU3
GPT
ICU
DTC
Data flash
WDT
IWDT
CRC
SCI 3 channels
RSPI
CAN (as an optional function)
LIN
POE3
CMT 2 channels (unit 0)
CMT 2 channels (unit 1)
RIIC
12-bit A/D converter 4 channels (unit 0)
Programmable gain amps
3 channels
Sample-and-hold circuits
for the pin section 3 channels
Window comparator 3 channels
12-bit A/D converter 4 channels (unit 1)
Programmable gain amps
3 channels
Sample-and-hold circuits
for the pin section 3 channels
Window comparator 3 channels
10-bit A/D converter 12 chan*n1 els
*1
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port A
Port B
Port D
Port E
Port G
[Legend]
POR: Power-on reset circuit
DTC: Data transfer controller
MTU3: Multi-function timer pulse unit 3
POE3: Port output enable 3
GPT: General PWM timer
CMT: Compare match timer
SCI: Serial communications interface
RIIC: I2C bus interface
MPU: Memory-Protection Unit
CAN: CAN module
LIN: LIN module
RSPI: Renesas serial peripheral interface
LVD: Voltage detection circuit
ICU: Interrupt controller
WDT: Watchdog timer
IWDT: Independent watchdog timer
CRC: CRC (cyclic redundancy check) calculator
Notes: 1. The installation of the 10-bit A/D converter and ports 1 to G is different depending on the package.
2. For details on the internal peripheral bus configuration, see section 12, Buses in the User’s manual:
Hardware.
Figure 1.2
Block Diagram
R01DS0096EJ0200 Rev.2.00
Jan 10, 2014
Page 12 of 134

12 Page





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