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PDF CLAA170EA07PY Data sheet ( Hoja de datos )
| Número de pieza | CLAA170EA07PY | |
| Descripción | Display Module | |
| Fabricantes | CHUNGHWA PICTURE TUBES | |
| Logotipo |  |
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CPT
CHUNGHWA PICTURES TUBES, LTD.,
f Chunghwa Picture Tubes, Ltd.
Technical Specification
To : STUDIO
Date : 2008.08.05
CPT TFT-LCD
CLAA170EA07P Y
ACCEPTED BY：
www.DataSheet.net/
APPROVED BY
KEVIN
CHECKED BY
LAWRENCE LAI
PREPARED BY
TFT-LCD Product
Planning Management
General Division
CHUNGHWA PICTUER TUBES, LTD.
1127 Hopin Rd., Padeh, Taoyuan, Taiwan 334, R.O.C.
TEL: +886-3-3675151 FAX: +886-3-377-3001
Doc.No: CLAA170EA07P Y-STUDIO-2008/08/05 Issue Date: 2008/08/05
CPT Confidential
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CLAA170EA07P Y-HAO SHENG-2008/08/05
www.yslcd.com.twDatasheetpdf-http://www.DataSheet4U.co.kr/
1 page  
CPT
2. ABSOLUTE MAXIMUM RATINGS
CHUNGHWA PICTURES TUBES, LTD.,
ITEM
SYMBOL MIN. MAX. UNIT
REMARK
Power Supply Voltage for LCD VCC 0 6.5
V
--
Lamp Voltage
VL 590 832 Vrms
Lamp Current
IL 3 8.0 mArms *4), 7)
Lamp Frequency
FL 40 80 kHz
static electricity
Operation Temperature
Storage Temperature
Delayed Discharge Time
VESDt
VESDC
Top
Tstg
TD
-200
-8000
0
-20
--
200
8000
50
60
1
V
V
℃
℃
Sec
5)
*1),2),3),6)
*1),2),3)
*8)
[Note]
1) The relative temperature and humidity range are as below sketch, 90%RHMax.(Ta≦40℃).
2) The maximum wet bulb temperature ≦39℃(Ta＞40℃) and without dewing.
3) If you use the product in a environment which over the definition of temperature and humidity
too long to effect the result of eye-atching.
4) The life time of the lamp is relate to the current of the lamp, so please accronding to the
description of the “(b) backlight” on page 7.
5) Test Condition: IEC 1000-4-2
VESDt: Contact discharge to input connector; VESDC: Contact discharge to module
6) If you operate the product in normal temperature range, the center surface of panel should be
under 60℃.
7) When lamp current is out of the absolute maximum range, the life will fall rapidly or shown
unusual sign.
IL min 2mA only for test only, but we can’t guarantee the lifetime and performance.
8) Delay lighting testing needs the volt above start volagte Vrms.Before the procedure tube needs
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typical lighting for 1 minute and stay in the temperature 25±2℃ for 24 hours and then testing
in the same condition in dark room .
90 Operating Range
(40,90)
80
Storage Range
60
(50,50.4)
40
(60,27.7)
20
5
-20 0 20 40 50 60
Temperature(°C)
CPT Confidential
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5 Page 
CPT
CHUNGHWA PICTURES TUBES, LTD.,
5. INTERFACE TIMING
(1) Timing Specifications
ITEM
SYMBOL MIN TYP MAX
DCLK
Frequency
Period
fCLK
45
54
70
tCLK 14.3 18.5 22.2
Horizontal Active Time
tHA
640
640
640
LCD
Horizontal Blank Time tHB 112 204 390
Timing
Horizontal Total Time tH 752 844 1030
DENA Vertical Active Time
tVA 1024 1024 1024
Vertical Blank Time
tVB 22 42 76
Vertical Total Time
tV 1046 1066 1100
Vertical Frame Rate
Fr 55 60 75
[Note]
1) DENA should always be positive polarity as shown in the timing specification.
2) CLK INshould appear during all blanking period,
3) Using LVDS IC
Receiver
DS90C384MTD(NS)
SN75LVDS82(TI)
Transmitter
DS90C383MTD(NS)
SN75LVDS83(TI)
UNIT
MHz
ns
tCLK
tCLK
tCLK
tH
tH
tH
Hz
4) Required signal assignment for flat link transmitter
Pin No. Pin Name
1 VCC
2 D5
3 D6
4 D7
5 GND
6 D8
7 D9
8 D10
9 VCC
10 D11
11 D12
12 D13
13 GND
14 D14
15 D15
16 D16
17 VCC
18 D17
19 D18
20 D19
21 GND
22 D20
23 D21
24 D22
25 D23
26 VCC
27 D24
28 D25
Require Signal
Power Supply for TTL Input
TTL Input (R7)
TTL Input (R5)
TTL Input (G0)
Ground pin for TTL
TTL Input (G1)
TTL Input (G2)
TTL Input (G6)
Power Supply for TTL Input
TTL Input (G7)
TTL Input (G3)
TTL Input (G4)
Ground pin for TTL
TTL Input (G5)
TTL Input (B0)
TTL Input (B6)
Power Supply for TTL Input
TTL Input (B7)
TTL Input (B1)
TTL Input (B2)
Ground pin for TTL
TTL Input (B3)
TTL Input (B4)
TTL Input (B5)
TTL Input (LVDS)
Power Supply for TTL Input
TTL Input (HSYNC)
TTL Input (VSYNC)
Pin No.
29
30
31
32
33
34www.DataSheet.net/
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Pin Name
GND
D26
TxCLKIN
PWR DWN
PLL GND
PLL VCC
PLL GND
LVDS GND
TxOUT3+
TxOUT3-
TxCLKOUT+
TxCLKOUT-
TxOUT2+
TxOUT2-
LVDS GND
LVDS VCC
TxOUT1+
TxOUT1-
TxOUT0+
TxOUT0-
LVDS GND
D27
D0
D1
GND
D2
D3
D4
Require Signal
Ground pin for TTL
TTL Input(DE)
TTL Level clock Input
Power Down Input
Ground pin for PLL
Power Supply for PLL
Ground pin for PLL
Ground pin for LVDS
Positive LVDS differential data output 3
Negative LVDS differential data output 3
Positive LVDS differential clock output
Negative LVDS differential clock output
Positive LDVS differential data output 2
Negative LVDS differential data output 2
Ground pin for LVDS
Power Supply for LVDS
Positive LVDS differential data output 1
Negative LVDS differential data output 1
Positive LVDS differential data output 0
Negative LVDS differential data output 0
Ground pin for TTL
TTL Input (R6)
TTL Input (R0)
TTL Input (R1)
Ground pin for TTL
TTL Input (R2)
TTL Input (R3)
TTL Input (R4)
CPT Confidential
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CLAA170EA07P Y-STUDIO-2008/08/05
www.yslcd.com.twDatasheetpdf-http://www.DataSheet4U.co.kr/
11 Page | ||
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