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PDF AD7570 Data sheet ( Hoja de datos )
| Número de pieza | AD7570 | |
| Descripción | CMOS 10-Bit Monolithic A/D Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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r. ANALOG
8 L.III DEVICES
CMOS
10-BitMonolithiAc ID Converter
FEATURES
8- and 10-Bit Resolution
20llS Conversion Time
Microprocessor Compatibility
Very Low Power Dissipation
Parallel and Serial Outputs
Ratiometric Operation
TTL/DTL/CMOS Logic Compatibility
CMOS Monolithic Construction
O8 BGENERAL DESCRIPTION
SThe AD7570 is a monolithic CMOS 10-bit successive approxi-
mation AID converter on a 120 by 13 5 mil chip, requiring
Oonly an external comparator, reference and passive clocking
components. Ratiometric operation is inherent, since an ex-
8 Ltremely accurate multiplying DAC is used in the feedback loop.
EThe AD7570 parallel output data lines and Busy line utilize
Tthree-state logic to permit bussing with other AID output and
Econtrol lines or with other I/O interface circuitry. Two enables
FUNCTIONAL DIAGRAM
OUT1
OUT2
AIN
VREF
I
I
10
,..,....--0 DB9 (MSB)
DB8
are available: one controls the two MSBs; the second controls
18
DB1
the remaining 8 LSBs. This feature provides the control interface
for most microprocessors which can accept only an 8-bit byte.
The AD7570 also provides a serial data output line to be used
in conjunction with the serial synchronization line. The clock
CaMP
8 can be driven externally or, with the addition of a resistor and
a capacitor, can run internally as high as 0.6MHz allowing a
STRT
total conversion time (8 bits) of typically 201ls. An 8-bit short
ClK
cycle control pin stops the clock after exercising 8 bits, nor-
mally used for the "J" version (8-bit resolution).
SUCCESSIVE
APPROXIMATION
lOGIC
19
DBO (lSBI
28
BUSY
8
SRO
27
BSEN
20
HBEN
21
lBEN
9
- SYNC
The AD7570 requires two power supplies, a +15V main supply
and a +5V (for TTL/DTL logic) to + 15V (for CMOS logic)
supply for digital circuitry. Both analog and digital grounds
are available.
L-221-13l-1l-6T-
-l
220 236 16 66
Vcc DGND voo AGND
The AD7570 is a monolithic device using a proprietary CMOS
process featuring a double layer metal interconnect, on-chip
thin-film resistor network and silicon nitride passivation
ensuring high reliability and excellent long term stability.
8
Information furnished by Analog Devices is believed to be accurate
and reliable. However, no responsibility is assumed by Analog Devices
for its use; nor for any infringementS of patents or other rights of third
parties which may result from its use. No license is granted by implica-
tion or otherwise under any patent or patent rights of Analog Devices.
P.O. Box 280; Norwood, Massachusetts 02062 U.S.
Tel:617/329-4700
Twx: 710/394-65'
Telex: 924491
Cables: ANALOG NORWOODMA:
--
1 page  
PIN FUNCTION DESCRIPTION
8 INPUT CONTROLS
8. Vcc (pin 22)
Vcc is the logic power supply. If +5V is used, all control
inputs/outputs (with the exception of comparator terminal)
1. Convert Start (pin 25 - STRT)
When the start inpu t goes to Logical" 1 ", the MS B data
are DTL/TTL compatible. If +15V is applied, control
inputs/outputs are CMOS compatible.
latch is set to Logic "1" and all other data latches are set to
Logic "0". When the start input returns low, the conversion
OUTPUT FUNCTIONS
sequence begins. The start command must remain high for
at least 500 nanoseconds. If a start command is reinitiated
1. Busy (pin 28 - BUSY)
during conversion, the conversion sequence starts over.
The Busy line indicates whether conversion is complete or
2. High Byte Enable (pin 20 - HBEN)
This is a three-state enable for the bit 9 (MSB) and bit 8.
in process. Busy is a three-state output and floats until the
Busy-Enable line is addressed with a Logic "1 ". When
When the control is low, the output data lines for bits
9 and 8 are floating. When the control is high, digital
addressed, Busy will indicate either a "1" (conversion com-
plete) or a "0" (conversion in process).
data from the latches appears on the data lines.
2. Serial Output (pin 8 - SRO)
3. Low Byte Enable (pin 21 - LBEN)
Same as High Byte Enable pin, but controls bits 0 (LSB)
through 7.
Provides output data in serial format. Data is available only
during conversion. When the A/D is not converting, the
Serial Output line "floats." The Serial Sync (see next func-
tion) must be used, along with the Serial Output terminal
8~ 4. Busy Enable (pin 27 - BSEN)
to avoid misinterpreting data.
This is an interrogation input which requests the status of
Othe converter, i.e., conversion in process or convert com-
plete. The converter status is addressed by applying a Logic
B"1" to the Busy Enable. (See Busy under Output Functions.)
3. Serial Synchronization (pin 9 - SYNC)
Provides 10 positive edges, which are synchronized to the
Serial Output pin. Serial Sync is floating if conversion is
not taking place.
S5. Short Cycle 8 Bits (pin 26 - SCS)
With a Logic "0" input, the conversion stops after 8 bits
Oreducing the conversion time by 2 clock periods. This
Note that all digital inputs/outputs are TTL/DTL compatible
when Vcc is +5V, and CMOS compatible when VCC is +15V.
<8 Lcontrol should be exercised for proper operation of the "J"
version. When a Logic "1" is applied, a complete 10-bit con-
Eversion takes place ("L" version).
TE6. Clock (pin 24 - CLK)
PIN
NO. MNEMONIC
FUNCTION
With an external RC connected, as shown in the figure
below, clock activity begins upon receipt of a Convert-Start
1 VDD
Positive Supply (+ 15V)
command to the A/D and ceases upon completion of con-
version. An external clock (CMOS or TTL/DTL levels) can
directly drive the clock terminals, if required. Figure 2
shows the internal CLK frequency versus Rand C. If Vcc
2 VREF
3 AIN
4 oun
5 OUT2
6 AGND
Voltage REFerence (:t10V)
Analog INput
DAC Current OUTput 1
DAC Current OUTput 2
Analog GrouND
8~
is <4.75V, the internal CLK will not operate.
7 COMP
8 SRO
COMParator
SeRial Output
9 SYNC
Serial SYNChronization
10 DB9
Data Bit 9 (MSB)
+5V
(
11 DB8
12 DB7
13 DB6
Data Bit 8
Data Bit 7
Data Bit 6
R
AD7570
24
14 DB5
15 DB4
16 DB3
17 DB2
18 DB1
Data Bit 5
Data Bit 4
Data Bit 3
Data Bit 2
Data Bit 1
8~
CI
Generating Internal Clock Frequency
7. VDD (pin 1)
VDD is the positive supply for all analog circuitry plus some
19 DBO
20 HBEN
21 LBEN
22 VCC
23 DGND
24 CLK
25 STRT
26 SC8
27 BSEN
28 BUSY
Data Bit 0 (LSB)
High Byte ENable
Low Byte ENable
Logic Supply (+ 5V to + 15V)
Digital GrouND
CLocK
STaRT
Short Cycle 8 Bits
BuSy ENable
BUSY
digital logic circuits that are not part of the TTL compatible
input/output lines (back-gates to the P-channel devices).
Nominal supply voltage is +15V.
Table 1. Function Table
-5-
5 Page 
8
MICROPROCESSOR INTERFACE
Since most 8-bitmicroprocessors
utilize a bidirectio~al data
bus, each input peripheral (such as the AD7570) must be
capable of isolating itself from the data bus when other I/O
devices, memory, or the CPU takes control of the bus. The
AD7570 output data and status (BUSY) lines all utilize three-
state logic to provide this requirement.
Figure 16 illustrates a method of interfacing a TTY keyboard
and printer to the AD7570, using an 8080 microprocessor as
the interface controller.
3. LBEN is enabled, and the eight least significant data bits
(DBO-DB7) are applied to the data bus for subsequent trans-
fer to the 8080. When the data transfer is complete, LBEN
is disabled, and DBO-DB7 return to their floating state.
4. HBEN is enabled, and the two most significant AD7570 data
bits (DB8 and DB9) are applied to the data bus for subse-
quent transfer to the 8080. When the data transfer is
complete, HBEN is disabled, and DB8 and DB9 return to
their floating state.
The program (stored in Read Only Memory) waits for a key-
stroke on the TTY keyboard. When a keystroke is detected,
5. The 8080 (in conjunction with the programmed Read Only
Memory) performs a binary to decimal conversion.
an AID conversion is started. When conversion is complete,
the 8080 reads in the binary data from the AD7570, converts
6. SWE (Status Word Enable) on the UAR/T transmitter is
it to ASCII, and prints out the decimal number (preceded by a
carriage return and line feed) on the teletype printer.
enabled, applying XBMT (Transmitter Buffer Empty) to
the data bus. When a Logic "1" is detected by the 8080,
SWEis disabled, and XBMT returns to a floating state.
More specifically, the main sequence of events would be as
follows:
~
7. TDS (Transmitter Data Strobe) strobes the converted
8 1. When a TTY keystroke is detected by the CPU (via the
decimal number into the UAR/T transmitter for subsequent
OUAR/T Receiver), a "convert start" (STRT) is applied to
serial clocking into the keyboard.
the AD7570.
B2. BSEN is enabled, placing BUSY (conversion status) on the
Sdata bus. When the 8080 detects BUSY = 1, conversion is
Ocomplete, and BSEN is disabled, causing BUSY to return to
its floating state.
The interface scheme shown below is only one example of a
myriad of possible data acquisition/control systems which
could conveniently use the AD7570 to provide digital data to
a microprocessor or minicomputer bus.
8 LE~
TEA15
A8 DBFLlN . MEMR . A2
A7
ADDRESS BUSS
I
DBFLlN . MEMR . A4
AO DBFLlN
8~
8080
DO-D7
BSEN
HBEN
AD7570 ADC
(MSBI
(lSB)
-, ,BOSY DB9 8 7 6 5 4 3 2 1 BDO
DBFLlN . MEMR
DATA BUSS
DO DO
DO
D7
D1 DO D7 D6
Dol 07'
03 D2 D1 DO
8.
WR
DBFLlN
SYNC
FROM
KEYBOARD
RDA
RSI
UAR/T REC
RDAR RDE SWE
XBMT
UAR/T XMT
TDS
.WR AO
DBFLlN
WR A2
TO PRINTER
.. MEMR AO
DBFLlN . MEMR . AT
D
ClK
:J1 . SYNC
MEMR
Q
O.MEMR
Figure 16. Microprocessor Controlled TTY IADC Interface
-11-
..
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet AD7570.PDF ] | |
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