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PDF CY7C0241 Data sheet ( Hoja de datos )
| Número de pieza | CY7C0241 | |
| Descripción | 4K x 16/18 and 8K x 16/18 Dual-Port Static RAM | |
| Fabricantes | Cypress Semiconductor | |
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CY7C024/024A/0241
CY7C025/0251
4K x 16/18 and 8K x 16/18 Dual-Port
Static RAM with SEM, INT, BUSY
Features
■ True dual-ported memory cells, which allow simultaneous
reads of the same memory location
■ 4K x 16 organization (CY7C024/024A[1])
■ 4K x 18 organization (CY7C0241)
■ 8K x 16 organization (CY7C025)
■ 8K x 18 organization (CY7C0251)
■ 0.65 micron CMOS for optimum speed and power
■ High speed access: 15 ns
■ Low operating power: ICC = 150 mA (typ)
■ Fully asynchronous operation
■ Automatic power down
■ Expandable data bus to 32/36 bits or more using Master/Slave
chip select when using more than one device
■ On-chip arbitration logic
■ Semaphores included to permit software handshaking
between ports
■ INT flag for port-to-port communication
■ Separate upper-byte and lower-byte control
■ Pin select for Master or Slave
■ Available in 84-pin (Pb-free) PLCC, 84-pin PLCC, 100-pin
(Pb-free) TQFP, and 100-pin TQFP
Functional Description
The CY7C024/024A/0241 and CY7C025/0251 are low power
CMOS 4K x 16/18 and 8K x 16/18 dual-port static RAMs. Various
arbitration schemes are included on the CY7C024/ 0241 and
CY7C025/0251 to handle situations when multiple processors
access the same piece of data. Two ports are provided,
permitting independent, asynchronous access for reads and
writes to any location in memory. The CY7C024/ 0241 and
CY7C025/0251 can be used as standalone 16 or 18-bit dual-port
static RAMs or multiple devices can be combined to function as
a 32-/36-bit or wider master/ slave dual-port static RAM. An M/S
pin is provided for implementing 32-/36-bit or wider memory
applications without the need for separate master and slave
devices or additional discrete logic. Application areas include
interprocessor/multiprocessor designs, communications status
buffering, and dual-port video/graphics memory.
Each port has independent control pins: Chip Enable (CE), Read
or Write Enable (R/W), and Output Enable (OE). Two flags are
provided on each port (BUSY and INT). BUSY signals that the
port is trying to access the same location currently being
accessed by the other port. The Interrupt Flag (INT) permits
communication between ports or systems by means of a mail
box. The semaphores are used to pass a flag, or token, from one
port to the other to indicate that a shared resource is in use. The
semaphore logic is comprised of eight shared latches. Only one
side can control the latch (semaphore) at any time. Control of a
semaphore indicates that a shared resource is in use. An
automatic power down feature is controlled independently on
each port by a chip select (CE) pin.
The CY7C024/024A/0241 and CY7C025/0251 are available in
84-pin Pb-free PLCCs, 84-pin PLCCs (CY7C024 and CY7C025
only), 100-pin Pb-free Thin Quad Plastic Flatplack (TQFP), and
100-pin Thin Quad Plastic Flatpack.
Note
1. CY7C024 and CY7C024A are functionally identical.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-06035 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised December 09, 2008
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CY7C024/024A/0241
CY7C025/0251
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches (CE
must remain HIGH during SEM LOW). A0–2 represents the
semaphore address. OE and R/W are used in the same manner
as a normal memory access. When writing or reading a
semaphore, the other address pins have no effect.
When writing to the semaphore, only I/O0 is used. If a zero is
written to the left port of an available semaphore, a one appears
at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing zero
(the left port in this case). If the left port now relinquishes control
by writing a one to the semaphore, the semaphore is set to one
Table 1. Non-Contending Read/Write
for both sides. However, if the right port had requested the
semaphore (written a zero) while the left port had control, the
right port immediately owns the semaphore as soon as the left
port released it. Table 3 shows sample semaphore operations.
When reading a semaphore, all sixteen/eighteen data lines
output the semaphore value. The read value is latched in an
output register to prevent the semaphore from changing state
during a write from the other port. If both ports attempt to access
the semaphore within tSPS of each other, the semaphore is
definitely obtained by one side or the other, but there is no
guarantee which side controls the semaphore
Inputs
CE R/W OE UB
LB SEM
Outputs
I/O0–I/O7[3]
I/O8–I/O15[4]
Operation
HXXX
X
H High Z
High Z
Deselected: Power Down
XXXH
H
H High Z
High Z
Deselected: Power Down
L L X L H H High Z
Data In
Write to Upper Byte Only
L LXH
L
H Data In
High Z
Write to Lower Byte Only
LLXL
L
H Data In
Data In
Write to Both Bytes
L H L L H H High Z
Data Out
Read Upper Byte Only
LHLH
L
H Data Out
High Z
Read Lower Byte Only
LHL L
L
H Data Out
Data Out
Read Both Bytes
XXHX
X
X High Z
High Z
Outputs Disabled
HHL X X
L Data Out
Data Out
Read Data in Semaphore Flag
XH L H
H
L Data Out
Data Out
Read Data in Semaphore Flag
H
XX
X
L Data In
Data In
Write DIN0 into Semaphore Flag
X
XH
H
L Data In
Data In
Write DIN0 into Semaphore Flag
L XX L
LXXX
X
L
L
L
Not Allowed
Not Allowed
Table 2. Interrupt Operation Example (Assumes BUSYL=BUSYR=HIGH)[7]
Function
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
Reset Left INTL Flag
R/WL
L
X
X
X
Left Port
CEL
L
OEL
X
A0L–11L
(1)FFF
XX
X
XX
X
L L (1)FFE
INTL
X
X
L[8]
H[9]
R/WR
X
X
L
X
Right Port
CER
X
OER
X
A0R–11R
X
L L (1)FFF
L X (1)FFE
XX
X
INTR
L[9]
H[8]
X
X
Document #: 38-06035 Rev. *D
Page 5 of 21
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CY7C024/024A/0241
CY7C025/0251
Switching Waveforms
Figure 4. Read Cycle No. 1 (Either Port Address Access)[23, 24, 25]
ADDRESS
DATA OUT
tAA
tOHA
PREVIOUS DATA VALID
tRC
DATA VALID
tOHA
CE and
LB or UB
OE
DATA OUT
ICC
CURRENT
ISB
ADDRESS
UB or LB
CE
DATA OUT
Figure 5. Read Cycle No. 2 (Either Port CE/OE Access)[23, 26, 27]
tACE
tDOE
tLZOE
tLZCE
tPU
tHZCE
tHZOE
DATA VALID
tPD
Figure 6. Read Cycle No. 3 (Either Port)[23, 25, 26, 26, 27]
tRC
tAA tOHA
tLZCE
tABE
tACE
tLZCE
tHZCE
tHZCE
Notes
23. R/W is HIGH for read cycles
24. Device is continuously selected CE = VIL and UB or LB = VIL. This waveform cannot be used for semaphore reads.
25. OE = VIL.
26. Address valid prior to or coincident with CE transition LOW.
27. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.
Document #: 38-06035 Rev. *D
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| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet CY7C0241.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
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